Basal Plane Dislocation Density Research Articles

The Numerical Simulations and Experimental Study of an 8-Inch SiC Single Crystal with Reduced BPD Density.

The basal plane dislocation (BPD) density is one of the most important defects affecting the application of SiC wafers. In this study, numerical simulations and corresponding experiments were conducted to investigate the influence of cooling processes, seed-bonding methods, and graphite crucible materials on the BPD density in an 8-inch N-type 4H-SiC single crystal grown by the physical vapor transport (PVT) method. The results showed that the BPD density could be effectively reduced by increasing the cooling rate, optimizing the seed-bonding method, and adopting a graphite crucible with a similar coefficient of thermal expansion as the SiC single crystal. The BPD density in the experiments showed that a high cooling rate reduced the BPD density from 4689 cm-2 to 2925 cm-2; optimization of the seed-bonding method decreased the BPD density to 1560 cm-2. The BPD density was further reduced to 704 cm-2 through the adoption of a graphite crucible with a smaller thermal expansion coefficient.

Suppression of In-Grown SF Formation and BPD Propagation in 4H-Sic Epitaxial Layer by Sublimating Sub-Surface Damage before the Growth

It is known that basal plane dislocations (BPDs) and in-grown stacking faults (IGSFs) in the 4H-SiC epitaxial layer cause severe electrical degradation in SiC devices. The impact that sub-surface damage (SSD) on a production-grade 4H-SiC substrate with CMP-finished surface causes on both the BPD propagation and IGSF formation during epitaxial growth was investigated by Dynamic AGE-ing (DA). The substrates etched by DA sublimation etching to adjust the residual amount of SSD maintaining a smooth surface without macro step bunching were grown to observe BPD and IGSF density. The obtained results showed that these defect densities decreased exponentially with increasing etching depth. We demonstrated SSD introduced by mechanical processing led BPDs and IGSFs to extend or introduce to the epitaxial layer.

Demonstrations of high voltage SiC materials, devices and applications in the solid state transformer

High voltage SiC power devices have been proven as the potential candidates in replacing the Si counterparts to improve the overall power converting efficiency of the power grids and power systems. In this paper, the demonstrations of high voltage materials and devices along with the applications in the power electronic transformer are presented. Through optimizing the temperature and pressure fields, the grown wafer is totally 4H-SiC and no foreign type exists. The FWHM (Full Width at Half Maximum) of the X-ray rocking curve is 23 arcsec, which indicates a high crystalline quality. Moreover, a thick epitaxial layer is then grown on the wafer. The BPD (Basal Plane Dislocation) density of the epitaxial layer is eliminated by converting the BPD to TED (Threading Edge Dislocation) through a proposed doping-induced defect evolution technology. Furthermore, the high voltage SiC MOSFETs with a blocking voltage of over 6.5 kV are fabricated by optimizing the cell and termination structures. The channel region and JFET region are optimized to further improve the device performance. The typical current conducting capability of a single MOSFET is up to 25 A and the breakdown voltage reaches 7.8 kV at a leakage current of 10 μA. The devices are then packaged to form the 6.5 kV/400 A power modules. The current balancing and thermal designs are taken into consideration to improve the reliability of power modules. Finally, the developed SiC modules are applied in a solid state transformer to demonstrate the advantages of SiC devices. The work presented in this article provides an important guide in developing high voltage and high current SiC power devices.

(Invited) Physical Understanding and Prevention of Bipolar Degradation in SiC Power Devices

Through recent progress in SiC technology, 1–3 kV-class SiC power devices (field effect transistors and Schottky barrier diodes) have been commercialized, demonstrating remarkable reduction of power dissipation in various electric systems. However, “bipolar degradation” caused by forward conduction of pn junctions has not been completely solved [1]. In this paper, physical understanding and prevention of the bipolar degradation in SiC devices are reviewed.Degradation in SiC bipolar devices is caused by expansion of a single Shockley-type stacking fault (SSF) in {0001} from a basal plane dislocation (dislocations lying on a {0001} plane) through minority carrier injection and subsequent recombination [2]. The authors conducted careful observation and theoretical analyses on the shapes of expanded SSFs in SiC upon minority carrier injection, and clarified 36 different types of SSFs [3]. For fabrication of high-reliability SiC devices, any basal plane dislocations must be eliminated from a lightly-doped voltage-blocking layer, where a high density of excess carriers is injected during device operation. The authors carried out a number of SiC epitaxial growth runs by using a custom-made chemical vapor deposition system and discovered that almost all the basal plane dislocations can be converted to threading edge dislocations in the initial stage of SiC epitaxial growth (dislocation conversion occurs near the epilayer/substrate interface). The typical density of basal plane dislocations in SiC epitaxial layers was 1–10 cm-2, but the density could be reduced to 0.1 cm-2 or less by increasing the growth rate from 5 to 24 µm/h on 4 degrees off-axis SiC(0001) substrates without any conflicts in the surface morphology and doping control (see the attached image). The achieved dislocation density (< 0.1 cm-2) is low enough to fabricate 1 cm2 devices (300–400 A devices) free from the degradation phenomenon. A basal plane dislocation and a threading edge dislocation can possess the same Burgers vector, which is the reason why the dislocation conversion can take place. It is also noted that a threading edge dislocation, which runs along <0001> (perpendicular to the {0001} plane), does not affect the performance and reliability of SiC devices, at least, within operation conditions in practical applications.It has been experimentally revealed that a SSF can either expand or contract, depending on the current density and temperature. Thus, it is essential to clarify the critical condition where SSF expansion starts. The authors developed a physics-based model to calculate the effective formation energy of a SSF in SiC, taking account of the electronic energy gain by forming a SSF under minority carrier injection [4]. Here a SSF exhibits a slightly smaller bandgap than the perfect SiC and a SSF behaves like a quasi-quantum well in SiC. It can be judged that SSF expansion takes place when the effective SSF formation energy is negative, by which the free energy is lowered by SSF expansion [5].The effective SSF formation energy was calculated as a function of the injected excess carrier density at different temperatures. When the carrier density is low, the SSF formation energy is close to the value in equilibrium (4.7 mJ/m2 [6]). As the carrier density increases, the SSF formation energy turns to be negative due to the electronic energy gain, and the critical excess carrier density above which SSF expansion occurs can be determined as about 5E14 cm-3 at 300 K from this calculation. This critical carrier density gradually increases with elevating the temperature, due to the enhanced emission of electrons from an SSF and thereby a lowered energy gain. The critical carrier density was experimentally determined through observation of SSFs in fabricated SiC pn diodes operating at different current densities and temperatures. The critical carrier density experimentally determined was 4E14 cm-3 at room temperature, being a very good agreement with the theoretical prediction mentioned above. Therefore, the developed model serves as a guideline for preventing bipolar degradation. Based on these results, nearly perfect prevention of bipolar degradation can be achieved by introducing a “recombination-enhancement layer” between a voltage-blocking layer and a substrate, the detail of which shall be explained at the conference.[1] T. Kimoto and H. Watanabe, Appl. Phys. Express, 13, 120101 (2020).[2] M. Skowronski and S. Ha, J. Appl. Phys., 99, 011101 (2006).[3] A. Iijima et al., Philos. Mag., 97, 2736 (2017).[4] A. Iijima and T. Kimoto, J. Appl. Phys., 126, 105703 (2019).[5] K. Maeda et al., Mater. Sci. Forum, 725, 35 (2012).[6] K. Maeda et al., Appl. Phys. Express, 14, 044001 (2021). Figure 1

Doping-dependent nucleation of basal plane dislocations in 4H-SiC

Basal plane dislocations (BPDs) are one of the most harmful dislocations in 4H silicon carbide (4H-SiC). Understanding the nucleation of BPDs is the basis of reducing the density of BPDs in 4H-SiC. In this work, we investigate the nucleation mechanism of BPDs, as well as the effect of doping on the nucleation of BPDs in 4H-SiC using nanoindentation. It is found that the shear stress plays a dominant role in the nucleation of BPDs in undoped 4H-SiC. This indicates that the shear component of the thermal stress during the growth of 4H-SiC single crystals and that of the mechanical stress during the processing of 4H-SiC wafers both give rise to the nucleation of BPDs. Nitrogen (N) doping is found to facilitate the nucleation of BPDs and decrease the shear stress required for the nucleation of BPDs. In contrast, vanadium (V) doping hinders the nucleation of BPDs, which promotes the polymorph transition from 4H-SiC to 3C-SiC.

Nucleation sites of expanded stacking faults detected by in operando x-ray topography analysis to design epitaxial layers for bipolar-degradation-free SiC MOSFETs

We investigated the nucleation sites of expanded single Shockley-type stacking faults (1SSFs) in a silicon carbide (SiC) metal–oxide–semiconductor field effect transistor (MOSFET) and demonstrated epitaxial layers designed for bipolar-degradation-free SiC MOSFETs. Since the sufficient hole density just below the basal plane dislocation (BPD)-threading edge dislocation (TED) conversion points induces 1SSF expansion, we derived the dependence of the nucleation depth on the applied current condition from the BPD-TED conversion points of 1SSFs. We first simulated and determined the three-step current conditions applied to a body diode in a SiC MOSFET so that a sufficient amount of holes would be supplied to the drift layer, to the buffer layer, and inside the substrate in the SiC MOSFET. An in operando x-ray topography analysis was conducted with the determined conditions for dynamically visualizing 1SSF expansion motions, and 1SSFs expanded at different forward current densities were successfully extracted. The depths of the BPD-TED conversion points of the extracted 1SSFs were analyzed, and it was experimentally clarified that these depths, i.e., the nucleation sites of expanded 1SSFs, became deeper with forward current densities. The bipolar degradation characteristics of SiC MOSFETs were evaluated as a function of the forward current density, and the validity of the simulation model was verified by experimental results. We also confirmed that bipolar degradation can be suppressed to some extent by using a substrate with a low BPD density, and SiC MOSFETs with a high-nitrogen-concentration epitaxial layer showed high reliability under bipolar operation. Depending on the application of SiC MOSFETs, the epitaxial layers should be designed to prevent the hole density inside the substrate from exceeding the threshold for 1SSF expansion.

(Invited) Updated Key Issues for SiC MOSFET Reliability

This work will provide an updated overview of our understanding of several key reliability issues for SiC power MOSFETs, including threshold-voltage stability, body-diode robustness, and short-circuit current robustness. We will also discuss recent results regarding the modeling of high-field breakdown in SiC and other power semiconductor devices.Threshold-voltage instability likely occurs due to the charging and discharging of near-interfacial oxide traps in response to a change in gate bias. If enough traps change charge state, it can lead to significant shifts in the threshold voltage, which may in turn lead to increases in leakage current in the off state, or increases in on-state resistance in the on state. An important question is, what is the best—or most appropriate—test method to use to determine the reliability of these devices. A key factor is the measurement speed used to determine the magnitude of the threshold-voltage instability. It has recently been observed that one commercial device manufacturer has large instabilities, even in previously unstressed devices, and that such large instabilities can result in significant increases in on-resistance during normal switching conditions, thereby degrading circuit performance.Some suppliers of SiC power MOSFETs are producing devices with low basal plane dislocation (BPD) density, resulting in decreased bipolar degradation during normal operation of its integral body-diode. However, not all suppliers manage their BPD densities to the same degree, resulting in a variation in responses observed across suppliers. Even devices from a single supplier with the same date code exhibited varying levels of degradation for identical body-diode stress and measurement conditions. Unlike other extended defects, BPDs when faulted, leads to degradation in both the body-diode and MOSFET characteristics. These faulted BPDs induce stacking faults that expand over time and limits the reliability of some commercially available SiC MOSFETs. This degradation phenomenon necessitates the development of an appropriate reliability test standard for SiC to separate good devices from bad ones. Three of the five major suppliers of 1200-V SiC MOSFETs showed varying levels of bipolar degradation in both their body-diode forward voltages and their MOSFET on-resistances. Two out of three suppliers of 1700-V SiC MOSFETs showed significant bipolar degradation issues with one particular supplier’s devices showing forward voltage changes of 1.3 V to 2.5 V from their pre-stress values. Their on-state resistance values were also significantly degraded.Another important aspect of SiC MOSFET reliability is its robustness to short-circuit current conditions that can occur in many power electronics applications utilizing a half-bridge topology. Since both planar and trench device architectures are commercially available, electrical results have been generated to highlight their short-circuit capabilities under similar circuit conditions. Our electrical results show that trench devices have lower robustness in comparison to planar devices of similar ratings. These differences in short-circuit withstand times can be attributed to the smaller heat conduction volume of the trench design coupled with its higher saturation drain current for the same gate-drive voltage. The existing test method for short-circuit withstand time in the MIL-STD may overestimate the actual withstand time because it relies on a single gate-pulse method. Electrical results indicate that an incremental gate-pulse method may be more accurate in determining the actual withstand time, and it has proven to be more effective in determining latent failures missed by the standard method.Another key issue for power devices in general is the trade-off between on-state resistance and blocking voltage. One of the key advantages of wide bandgap (WBG) materials such as SiC is that it can block the same voltage as Si using a much thinner, and more highly-doped, blocking layer. This results in a much lower on-state resistance at the same rated voltage. The superior high-field properties of WBG (and ultra WBG) power semiconductor materials also enable them to block much higher voltages than Si is able—as long as the background doping is low enough. We will present recent work, using impact ionization coefficients from the literature, to calculate avalanche breakdown as a function of epi-layer thickness and doping, thereby determining on-state resistance versus breakdown voltage for SiC and GaN. We will compare these results to Si, as well as to UWBG materials such as diamond, AlGaN, and Ga2O3. It is observed that SiC and GaN have very similar characteristics in terms of critical field, and in their relationships between on-state resistance and blocking voltage.

Progress in Bulk 4H SiC Crystal Growth for 150 mm Wafer Production

The thermoelastic stress, mechanical properties and defect content of bulk 4H n-type SiC crystals were investigated following adjustments to the PVT growth cell configuration that led to a 40% increase in growth rate. The resulting 150 mm wafers were compared with wafers produced from a control process in terms of wafer bow and warp, and dislocation density. Wafer shape was found to be comparable among the processes, indicating minimal impact on internal stress. Threading edge and threading screw dislocation densities increased and decreased, respectively, while basal plane dislocation densities were unaffected by the increase in growth rate. Loss of wafer planar stability was observed in certain cases. The elastic modulus was measured to be in the range of approximately 420-450 GPa for selected stable and unstable wafers, and was found to correspond to resistivity.

4H-SiC Epi-Ready Substrate Qualification by Using Mirror Electron Microscope Inspection System

Crystal damage beneath the surface remaining after chemo-mechanical polishing (CMP) and basal plane dislocations (BPDs) of 4H-SiC epi-ready substrates have been inspected by using a mirror electron microscope inspection system non-destructively. Distributions of crystal damage and BPDs as well as their average densities are estimated by acquiring 80-μm square mirror electron images at positions distributed with an equal pitch over a substrate (“Discrete point set inspection”). Although the total inspected area is less than 1% of the entire substrate area, the inspection results for nine commercially available wafers reveal that there are large differences in surface polishing quality and BPD density between them. Evaluation on an epitaxial layer with a thickness of 10 μm grown on one of the inspected substrates indicated that correlation between distribution of the crystal damages on the substrate and that of bunched steps on the epitaxial layer surface.

Evaluation of Suppressing Forward Voltage Degradation by Using a Low BPD Density Substrate or an Epitaxial Wafer with an HNDE

Forward voltage degradation is a crucial problem that must be overcome if we are to fabricate a metal-oxide semiconductor field-effect transistor (MOSFET) including a pin diode (PND) as a body diode in a silicon carbide (SiC). Previously, the basal plane dislocation (BPD) in a SiC substrate have been reduced to suppress bipolar degradation. On the other hand, an highly N-doped epilayer (HNDE) was recently fabricated that enhances the minority carrier recombination before the carrier arrives at the substrate. Although both approaches can reduce the Vf shift caused by the degradation, they should be used under different substrate conditions. When a substrate with a high BPD density is used for epitaxial growth, an HNDE is needed to realize a high-quality epitaxial wafer; however, the HNDE should not be formed on a substrate with a low BPD density.

Synchrotron X-Ray Topography Study on the Relationship between Local Basal Plane Bending and Basal Plane Dislocations in PVT-Grown 4H-SiC Substrate Wafers

Synchrotron monochromatic beam X-ray topography (SMBXT) in grazing incidence geometry shows black and white contrast for basal plane dislocations (BPDs) with Burgers vectors of opposite signs as demonstrated using ray tracing simulations. The inhomogeneous distribution of these dislocations is associated with the concave/convex shape of the basal plane. Therefore, the distribution of these two BPD types were examined for several 6-inch diameter 4H-SiC substrates and the net BPD density distribution was used for evaluating the nature and magnitude of basal plane bending in these wafers. Results show different bending behaviors along the two radial directions - [110] and [100] directions, indicating the existence of non-isotropic bending. Linear mapping of the peak shift of the 0008 reflection along the two directions was carried out using HRXRD to correlate with the results from the SMBXT measurements. Basal-plane-tilt angle calculated using the net BPD density derived from SMBXT shows a good correlation with those obtained from HRXRD measurements, which further confirmed that bending in basal plane is caused by the non-uniform distribution of BPDs. Regions of severe bending were found to be associated with both large tilt angles (95% black contrast BPDs to 5% white contrast BPDs) and abrupt changes in a and c lattice parameters i.e. local strain.

Effects of Pulsed and DC Body-Diode Current Stress on the Stability of 1200-V SiC MOSFET I-V Characteristics

1,200-V and 1,700-V SiC power MOSFETs from multiple suppliers were subject to dc and pulsed-current stress of the body-diode. Three of the five suppliers of 1,200-V devices evaluated showed no significant bipolar degradation, but the other two supplier’s devices showed varying degrees of degradation due this bipolar phenomenon. Electrical results of newly released 1,700-V devices from two suppliers showed significant degradation in the body-diode and MOSFET I-V characteristics following both dc and pulsed-current stress of their body-diodes. The electrical results presented in this work are consistent with basal plane dislocations (BPDs) that form stacking faults during forward conduction of the body-diode. Significant drift in the body-diode forward voltage and MOSFET on-resistance indicates that a much higher BPD density may be present in 1,700-V devices in comparison to the more mature 1,200-V device offerings. The likely presence of BPDs can lead to significant reliability issues in some modern SiC power MOSFETs, and their distribution seems to vary across suppliers and among devices with the same rating and from the same supplier. These differences are likely due to variations in wafer and device processing among suppliers and within a given product line from a single supplier.

X-ray topography characterization of gallium nitride substrates for power device development

Gallium nitride substrates grown by the hydride vapor phase epitaxy (HVPE) method using a patterned growth process have been characterized by synchrotron monochromatic beam X-ray topography in the grazing incidence geometry. Images reveal a starkly heterogeneous distribution of dislocations with areas as large as 0.3 mm2 containing threading dislocation densities below 103 cm−2 in between a grid of strain centers with higher threading dislocation densities (>104 cm−2). Basal plane dislocation densities in these areas are as low as 104 cm−2. By comparing the recorded images of dislocations with ray tracing simulations of expected dislocations in GaN, the Burgers vectors of the dislocations have been determined. The distribution of threading screw/mixed dislocations (TSDs/TMDs), threading edge dislocations (TEDs) and basal plane dislocations (BPDs) is discussed with implications for fabrication of power devices.

Relationship Between Basal Plane Dislocation Distribution and Local Basal Plane Bending in PVT-Grown 4H-SiC Crystals

The inhomogeneous distributions of basal plane dislocations (BPDs) in PVT-grown 4H-SiC crystal boule due to internal stresses cause lattice plane bending, which strongly affect SiC-based device fabrication. The relationship between BPDs and local basal plane bending in 6-inch 4H-SiC substrates has been investigated. Synchrotron monochromatic beam x-ray topography (SMBXT) imaging shows black and white contrast of BPDs with Burgers vectors of opposite signs based on the principle of ray tracing. We have evaluated the net difference of BPDs with black and white contrast along both [11$$ \bar{2}$$0] and [1$$ \bar{1}$$00] radial directions on the Si face across multiple 6-inch diameter 4H-SiC substrates sliced from the same and different boules and predicted the nature (concave/convex) and amount of bending of the basal plane in these wafers. Line scans of 0008 reflection using high resolution x-ray diffractometry (HRXRD) has been carried out along the two directions to verify the nature of bending in these wafers. Results show quite different bending behavior along [11$$ \bar{2} $$0] and [1$$ \bar{1}$$00] directions, indicating that the Si face of 6-inch substrates creates non-isotropic bending on the basal plane. These observations are correlated quite well with net BPD density analysis. The physical shapes of the wafers were also measured to be not flat due to the surface effect. Quantitative analysis of the degree of basal plane bending based on the SMBXT data was carried out and found to be correlating well with the measured tilt angle from HRXRD. Existence of a high stress center was observed in one of the 6-inch wafers resulting in severe bending which is associated with both large bending angles and abrupt changes in lattice constants a and c.

Effect of temperature on conversion of basal plane dislocations to treading edge dislocations during 4H-SiC homoepitaxiy

Abstract 4H-SiC homoepitaxial layer grown on 4° off-axis substrates is performed at various growth temperature by using the traditional chemical vapor deposition. The effect of growth temperature on propagation of basal plane dislocations from substrate to epitaxy was studied using the deep KOH etching and Synchrotron reflection X-ray topography, and the conversion mechanism was also investigated. It is found that the majority basal plane dislocations are converted to threading edge dislocations during epitaxial growth. Meanwhile, the two types of threading edge dislocations in epitaxial layer are observed after KOH etch. By the optimization of growth temperature, high quality epitaxial wafer with extremely low basal plane dislocations density (

High quality 4H-SiC homo-epitaxial wafer using the optimal C/Si ratio

Epitaxial growth of 4H-SiC on 4° off-axis substrates has been performed under different C/Si ratio in order to improve the quality level of epitaxial layer. 4H-SiC homoepitaxial layer is grown in horizontal warm-wall planetary reactor. The growth rate, doping concentration, morphology defect of epitaxial layer are characterized using the Fourier transform infrared, Hg schottky contact and optical surface analyzer, respectively. Meanwhile, the epitaxial layer is etched by molten KOH and microscopy observation to understand conversion of BPDs dependence of C/Si ratio. It is suggested that the defect density in the epitaxial layer is increased under C-rich and Si-rich condition, since the increasing of 2D island nucleation and formation of silicon drops, respectively. Moreover, this low conversion ratio is considered to be induced by suppression lateral growth under the low C/Si ratio condition. As a result, epitaxial layer with high yield (99.7%) and extremely low basal plane dislocations density (＜0.05 cm−2) can be obtained by the optimization of C/Si ratio.

Analysis of Basal Plane Dislocation Dynamics in PVT-Grown 4H-SiC Crystals during High Temperature Treatment

The deformation processes in 4H-SiC crystals are of particular interest because they generate mostly basal plane dislocations (BPDs) which are implicated in the degradation or premature breakdown of SiC power devices [1]. Fundamental understanding of the generation and multiplication of BPDs is critical for design of growth strategies to control the density of BPDs during PVT growth of 4H-SiC crystals. Recently, we reported on the direct observation of thermal gradient induced motion of BPDs through in-situ synchrotron X-ray topography imaging of PVT-grown 4H-SiC wafers subject to high temperature treatment [2]. The multiplication of BPDs by the operation and interactions of multiple Frank-Read sources leading to formation of complex configurations was reported. We have analyzed the series of images recorded during the in-situ experiment in detail to deduce the Burgers vectors and core structures of the moving dislocation segments and measure their individual velocities. Dislocations with Burgers vector along the off-cut 11-20 direction were found to be the only dislocations undergoing deformation during heat treatment. Sample was imaged after heat treatment and the segments of dislocations used for velocity measurements were found to be either pure screw or 60° dislocations comprised of Si cores. Using the kink-diffusion model, the activation energies for dislocation motion have been estimated from the velocity data for each of these dislocation types and found to be 2.21 eV for 60° and 3.28eV for pure screw segments respectively. These values are in good agreement with the macroscopic studies of yielding of semiconductor crystals during high temperature compression and indentation experiments [3,4]. Quantitative expression of the temperature dependent critical resolved shear stress required for dislocation motion has been derived from this analysis.

Dislocations Propagation Study Trough High-Resolution 4H-SiC Substrate Mapping

In this work a deep investigation of the dislocation on 4H-SiC substrate has been shown. The dislocation intersecting the surface were enhanced by KOH etching at 500 deg. C. performed on whole 6 inches substrate. A comparison between basal plane dislocations and threading screw dislocations in the substrate with the defects in the epitaxial layer (mainly stacking faults and carrots) was performed. The comparison between shows a correlation between basal plane dislocations density and stacking faults density maps.

Analysis of the Basal Plane Dislocation Density and Thermomechanical Stress during 100 mm PVT Growth of 4H-SiC.

Basal plane dislocations (BPDs) in 4H silicon carbide (SiC) crystals grown using the physical vapor transport (PVT) method are diminishing the performance of SiC-based power electronic devices such as pn-junction diodes or MOSFETs. Therefore, understanding the generation and movement of BPDs is crucial to grow SiC suitable for device manufacturing. In this paper, the impact of the cooldown step in PVT-growth on the defect distribution is investigated utilizing two similar SiC seeds and identical growth parameters except for a cooldown duration of 40 h and 70 h, respectively. The two resulting crystals were cut into wafers, which were characterized by birefringence imaging and KOH etching. The initial defect distribution of the seed wafer was characterized by synchrotron white beam X-ray topography (SWXRT) mapping. It was found that the BPD density increases with a prolonged cooldown time. Furthermore, small angle grain boundaries based on threading edge dislocation (TED) arrays, which are normally only inherited by the seed, were also generated in the case of the crystal cooled down in 70 h. The role of temperature gradients inside the crystal during growth and post-growth concerning the generation of shear stress is discussed and supported by numerical calculations.

Microstructure of Interfacial Basal Plane Dislocations in 4H-SiC Epilayers

As SiC power devices are being developed toward ultrahigh-voltage bipolar structures, the density of basal plane dislocations in SiC epilayers has to be minimized. In this work, a special category of basal plane dislocations, i.e. interfacial dislocations, was investigated. Their etch pits were detected at the interface and the microstructure was revealed by cross-section transmission electron microscope analysis.