Metal Barrier Layer Research Articles

CMP for Copper TSV Applications

AbstractThrough-silicon via (TSV) 3-D packaging and integration present many new opportunities and challenges for metals CMP applications. For front-side TSV polishing, challenges include the removal of large amounts of copper overburden, dishing control during copper clearing steps, and removal of large amounts of barrier metal and dielectric layers while still maintaining control over topography and defectivity. Additionally, the choice of barrier material can have significant impact on polishing in terms of the mechanical reliability regarding adhesion between the barrier metal and underlying dielectric layers. This paper will address many of these challenges with an emphasis on innovative technologies for superior process and endpoint controls, such as real-time profile control for thick copper films up to 6μm or more in thickness and automatic endpoint controls for barrier removal and dielectric stopping. The paper will also discuss some salient challenges for back-side TSV polishing, including the handling and polishing of bonded wafer pairs and strategies to minimize handling and polishing damage to the potentially fragile thinned device wafer. Additionally, the development of slurries with highly tunable copper-to-dielectric selectivity will be critical for enabling a wide range of final topographies, depending on requirements for subsequent bonding steps.

Effects of 2nd Phases, Stress, and Na at the Mo/Cu2ZnSnS4 Interface

AbstractCu2ZnSnS4 (CZTS) is an alternative material to Cu(In,Ga)Se2 (CIGSe) for use in thin film photovoltaic absorber layers composed solely of commodity elements [1,2]. Thus, if similar material quality and performance can be realized, its use would allow scale-up of terrestrial thin film photovoltaic production unhindered by material price or supply constraints. Here we report on our research on the deposition of CZTS by RF sputtering from a single CZTS target and co-sputtering from multiple binary sources on Mo-coated glass. We find some samples delaminate during post-sputtering furnace annealing in S vapor. Samples on borosilicate glass (BSG) delaminate much more frequently than those on soda-lime glass (SLG). We investigate the influences of the formation of frangible phases such as MoS2 at the CZTS/Mo interface and residual and thermal mismatch stress on delamination. We implicate fracture in a layer of MoS2 as the mechanism of delamination between the Mo and CZTS layers using scanning electron microscopy (SEM) and X-ray photoelectron spectroscopy (XPS). Wafer curvature measurements show significant (˜400 MPa) deposition stress for minimally optimized Mo deposition; however nearly stress-free Mo layers with good adhesion can be deposited using a multi-step Mo deposition recipe. Co-sputtering CZTS adds 100 MPa of stress on both BSG and SLG, however delamination is nearly absent for samples deposited on low-stress Mo layers. We investigate metallic diffusion barrier layers to prevent the formation of MoS2 at the interface. Lastly we discuss the importance of removing Mo oxide by sputter etching before CZTS deposition and its effects on adhesion and series resistance.

Dependence of the Fracture of PowerTrench MOSFET Device on Its Topography in Cu Bonding Process

Dependence of the fracture-resistance of a PowerTrench MOSFET device on its topography in Cu bonding process was investigated. Two different topographies, namely dimple and round, have been tested. A significantly higher cratering rate has been clearly observed on dimple topography. The dimple topography exhibited a cratering rate of 371 k ppm levels compared to 0 ppm in round topographies. Three-dimensional nonlinear finite-element analysis has shown that the largest compressive and shear stresses and their locations were identified, respectively, in borophosphosilicate glass (BPSG)/barrier metal layers of the dimple topography. The round topography had the smallest stress in BPSG/barrier metal layers. The higher compressive stress transferred to silicon in the dimple topography during the bonding process can induce a local crack, consequently causing silicon fracturing during the shearing processes. A significant improvement in the cratering performance was observed when the Al bond pad metal layer was reinforced by adding a barrier layer sandwiched in the Al metal layers. The cratering rate decreased to 1300 ppm levels. Additionally, the change in composition of a BPSG layer caused cratering was briefly discussed and an oxygen rich BPSG film in round topography was confirmed by the energy dispersive spectroscopy (EDS) of a cross-sectional TEM sample. It has been found that the cratering rate on dimple topography significantly increased from 1 k ppm to 100 k ppm levels, when the resulting residual Al pad thickness is less than 0.65 mum for Cu bonding performed with different ultrasonic (US) power and bond forces.

Novel Contact-Plug Process with Low-Resistance Nucleation Layer Using Diborane-Reduction Tungsten Atomic-Layer-Deposition Method for 32 nm Complementary Metal–Oxide–Semiconductor Devices and Beyond

The effect of employing diborane (B2H6) instead of silane (SiH4) in a tungsten (W) atomic layer deposition (ALD) nucleation layer on contact resistance is studied. A low resistance of 50–70 Ω in a 32-nm-node contact with a diameter of about 50 nm is achieved with optimized barrier and nucleation processes. This result indicates that the resistance required for 32 nm complementary metal–oxide–semiconductor (CMOS) devices can successfully be satisfied without employing a copper plug process. It is revealed that a W film with a B2H6-reduced nucleation layer has a larger grain size and a lower fluorine concentration in nucleation W and barrier metal layers, resulting in a lower resistivity than that with a SiH4-reduced nucleation W layer. On the other hand, the B2H6-reduced nucleation process still shows a poorer crystallization and a higher fluorine concentration in the filling W layer than the SiH4-reduced nucleation process. We revealed that a further decrease in the resistivity of a W film with the B2H6 nucleation process is achieved by improving these issues.

Controlling Ta phase in Ta/TaN bilayer by surface pre-treatment on TaN

Beyond 0.13 μm feature size, a bilayer of Ta/TaN is commonly used as a metal barrier and adhesive layer for copper multilevel interconnections. However, for the Ta films, cubic α-phase is preferred due to the lower resistivity, whereas high-resistive tetragonal β-phase should be avoided but easily formed by sputtering. Here, we demonstrate that the Ta overlayer phase can be effectively controlled by resputtering TaN surface using Ar prior to Ta growth. Upon surface treatment for enough time, α-phase forms instead of β-Ta. The intriguing phase change is attributed to the decrease of TaN lattice constant toward the surface, which renders a better lattice-matched template for α-Ta. From Auger depth profile, resputtering causes nitrogen deficiency in the surface layer of TaN to become TaN 0.1, leading to about 1.9% lattice mismatch. The mechanism for the phase change of the Ta overlayer was further verified by examining phase evolution of Ta deposited on various materials with different structure and lattice constants including W, TaN x ( x<1) and Ti.

Effect of sputtered Cu film’s diffusion barrier on the growth and field emission properties of carbon nanotubes by chemical vapor deposition

Growth of carbon nanotube (CNT) films with good field emission properties on glass is very important for low cost field emission display (FED) applications. In addition to Ni, Co and Fe, Cu can be a good catalyst for CNT growth on glass, but due to diffusion into SiO2 it is difficult to control the CNTs density and uniformity. In this paper, four metal barrier layers (W, Ni, Cr, Ti) were deposited by dc magnetron sputtering on glass to reduce the Cu diffusion. As-grown CNT films showed various morphologies with the use of different barrier metals. CNTs with uniform distribution and better crystallinity can be synthesized only on Ti/Cu and W/Cu. Voltage current measurements indicate that better field emission properties of CNT films can be obtained on titanium and tungsten barriered Cu, while chromium and nickel are not suitable barrier candidates for copper in CNT-FED applications because of the reduced emission performance.

Improved local thermal management of AlGaN-based deep-UV light emitting diodes

Local thermal management has a strong impact on the optical output power of AlGaN-based multiple-quantum-well deep-UV flip-chip light emitting diodes (LEDs). During the study, an improved methodology was developed by incorporating a metallic barrier layer of WSiN and a thermal interfacial layer of graphite/copper composite. The performance of these devices with improved thermal management and that of conventional flip-chip LEDs were compared. It was found that with the use of exotic material layers and modified Au–Sn bumps, the device heat dissipation capabilities were significantly enhanced. As a result, 70% enhancement in the optical output power of 250 µm disk LEDs (λ ∼ 287 nm) was observed with a better device thermal stability.

Interaction of copper organometallic precursors with barrier layers of Ti, Ta and W and their nitrides: a first-principles molecular dynamics study

Processes for the deposition of copper films on transition metal barrier layers by means CVD using organometallic precursors are often found to lead to poor adhesion characteristics of the grown film. By means of first-principles molecular dynamics simulations, we show that the source of the problem is the strong reactivity of the surfaces toward the precursors, which decompose spontaneously upon contact with the surface leading to contamination of the interface. Our simulations consider Ti, Ta, and W as barrier layers, and Cu(hfac)-(tmvs) as precursor. In contrast, we show that surfaces of these metals properly passivated with nitrogen, in such a way that only N atoms are exposed on the surface, are much less active and do not lead to decomposition of the precursor. We propose this passivation procedure as a practical solution to the adhesion problem.

Anatomy-performance correlation in Ti-based contact metallizations on AlGaN∕GaN heterostructures

A comprehensive study of the electrical and surface microstructural characteristics of Ti∕Au, Ti∕Al∕Au, Ti∕Mo∕Au, and Ti∕Al∕metal∕Au schemes, where metal is Ir, Mo, Nb, Pt, Ni, Ta, and Ti, has been carried out to determine the role of constituent components of multilayer contact metallizations on Ohmic contact formation on AlGaN∕GaN heterostructures. Attempts have been made to elucidate the anatomy (composition–structure) performance correlation in these schemes. Evidences have been obtained for the necessity of the Al and metal barrier layer as well as an optimal amount of Ti for achieving low-resistance Ohmic contact formation. A strong dependence of electrical properties and intermetallic interactions on the type of metal barrier layer used was found. Scanning electron microscopy characterization, coupled with energy dispersive x-ray spectroscopy, has shown evidence for alloy aggregation, metal layer fragmentation, Al–Au solid solution formation, and possible Au and/or Al reaction with metal layer. Results from the present study provide insights on the active and the necessary role various components of a multilayer contact metallization play for obtaining excellent Ohmic contact formation in the fabrication of AlGaN∕GaN high electron mobility transistors.

Cu (Ti) 合金微細配線における極薄バリア層の自己組織形成

Cu (Ti) 合金微細配線における極薄バリア層の自己組織形成

Effect of plasma process on low- k material and barrier layer performance

Low- k material is susceptible to the plasma damage in fabrication of damascene structure and hence the metal barrier performance will be affected. It is very important to characterize the effect of plasma process on metal barrier performance and fundamentally understand interfacial interaction between low- k material and metal barrier layer for implementing low- k, especially ultra low- k in Cu interconnect on 65 nm node and beyond. In this paper, we present our studies on the effects of two key plasma processes, H 2/He reactive plasma clean treatment (RPC) and H 2/N 2 etch, on the barrier layer performance. We also present a solution to enhance the Ta barrier layer performance. The new implementation successfully prevented Cu from diffusing into polymer low- k after annealing at 200 °C for 1000 h. The methodology is proven to be effective for characterizing and improving pore-sealing and barrier performance for Cu/porous ultra low- k interconnect.

Materials and Processes for Implementing High-Temperature Liquid Interconnects

This paper describes the results of a study investigating liquid solder joints at elevated temperatures (up to 200/spl deg/C). The reactions of eutectic 52In/48Sn solder, which melts at 118/spl deg/C, with various metal barrier layers is presented. The main emphasis of the research was to find a combination of solder and substrate metallization which has good adhesion strength but also remains stable during temperature cycling and high-temperature storage when the solder is molten. Intermetallic growth rates and solder-substrate adhesion strength have been measured for a range of potential barrier layers including Ni, Cr, Pt, Ti, V, Nb, Ta, and W. Of these, only Nb was found to have acceptable properties for a high-temperature barrier layer to In/Sn solder. Other aspects of liquid solder interconnections that have been studied include stability of the molten solder-underfill interface under electrical bias and retention of electrical contact during vibration and phase change. Plastic ball grid array (PBGA) devices have been assembled with Nb barrier layers and liquid solder joints and their reliability during temperature cycling (-20/spl deg/C to +180/spl deg/C) has been compared to PBGA joints with Sn95.5/Ag4/Cu0.5 solder balls.

Barrier studies on porous silk semiconductor dielectric

Barrier integrity of Ta-films deposited using the enhanced coverage by re-sputtering (EnCoRe 1 1 EnCoRe is a trademark of Applied Materials. ) barrier was investigated on untreated surfaces of blanket porous SiLK 2 2 SiLK is a trademark of The Dow Chemical Company. semiconductor dielectric (developmental version 7, hereinafter v7). Barrier integrity of a bi-layer EnCoRe Ta(N)/Ta film was studied on single damascene lines using v7 and porous SiLK semiconductor dielectric (developmental version 9, hereinafter v9). On blanket wafers more than 30 nm barrier thickness is necessary to achieve complete pore sealing. Analysis of the sheet resistance showed that when tantalum is deposited, a low resistivity α-phase is nucleated on the low- k surface. When deposited onto single damascene structures, EnCoRe Ta(N)/Ta is successful in providing a continuous metallic barrier layer over v7 and v9 semiconductor dielectric lines.

Erfahrungen bei der Querschnittspräparation von Schichtwerkstoffen mittels FIB-Methode / Experiences in Cross Section Preparation of Layered Materials by FIB-Method

In transmission electron microscopy (TEM) the quality of the images and the correctness of the results significantly depend on the specimen preparation. By the hand of various selected examples it is shown that the focused ion beammethod (FIB) as a nearly universal preparation technique is suitable for the high accuracy selected area preparation, and because of the relatively large electron transparent areas of uniform thickness, also for the valuation of the layered system quality. Furthermore the limitations of the FIB-method are shown, especially the Ga-implantation and amorphisation caused both by high energy Ga + - ions at the FIB cutting process and by the Pt-(Ga + )-covering onto the sample surface before the FIB cutting process. It is investigated, in what way in the latter case this effect can be avoided by additional metallic barrier layers covering the specimen. Eventually a technique is presented, at which the amorphisation layers formed at the thinning process are removed by low energy ion bombardment in a plasma cleaner.

Studies on Quantification Analysis of Thin Film Layers (Si3N4, SiO2, and TiW) in Wafer Fabrication Using Energy-Dispersive X-Ray Microanalysis Technique and SEC Factors

Abstract Currently standardless EDAX ZAF quantification method has been widely used in many new generation FESEM machines. This method is able to provide good and reliable elemental results for bulk samples and some films for some particles and contamination analysis, but for some cases, EDX results may not be accurate, especially for thin film layer identification in wafer fabrication. In this paper, standardless EDAX ZAF quantification method will be further studied and an EDX quantification analysis method with the SEC factor correction will be introduced. The SEC factors can be calculated using current EDAX software. Application results from passivation thin film Si3N4, SiO2 layers and barrier metal thin film TiW layer show that the EDX results have been greatly improved after performing the SEC factor correction and the relative error is greatly reduced from 64.3–101% to 0.23–3.93% for passivation Si3N4 layer, from 51.5–62.3% to 0.73–3.10% for passivation SiO2 layer and from 18.2–77.0% to 0.04–11.5% for barrier metal TiW layer. If we assume that the passivation and barrier metal layers always have a stoichiometric composition, this method could be used for the monitoring purpose in wafer fabrication.

Development and Application of an Abrasive-Free Polishing Solution for Copper

AbstractAn abrasive-free polishing (AFP) solution for chemical–mechanical planarization (CMP) of copper films on semiconductor wafers has been developed to overcome such disadvantages of conventional CMP as dishing, erosion, Cu and oxide loss, and microscratching. Electrochemical methods are an effective way of understanding the role of each chemical component in the AFP solution in order to optimize its performance. Analysis of the reaction layer of Cu elucidates the reasons for the excellent results that have been obtained. By applying the AFP solution for Cu CMP in combination with a slurry for CMP of the metal barrier layer, seven-level multilayer Cu interconnections can be successfully fabricated.

Positron Annihilation Lifetime Spectroscopy (Pals) Application in Metal Barrier Layer Integrity for Porous Low-K Materials

AbstractPositron Annihilation Lifetime Spectroscopy (PALS) (1, 2) is a useful tool to pre-screen metal barrier integrity for Si-based porous low-k dielectrics. Pore size of low-k, thickness of metal barrier Ta, positronium (Ps) leakage from PALS, trench sidewall morphology, electrical test from one level metal (1LM) pattern wafer and Cu diffusion analysis were all correlated. Macro-porous low-k (pore size &gt;= 200A) and large scale meso-porous low-k (&gt;50∼200A) encounter both Ps leakage and Cu diffusion into low-k dielectric in the 0.25μmL/0.3μmS structures when using SEMATECH in-house PVD Ta 250A as barrier layer. For small scale meso-porous (&gt;20∼50A) and micro-porous (&lt;=20A) low-k, no Ps leakage and no Cu diffusion into low-k were observed even with PVD Ta 50A, which is proved also owing to sidewall densification to seal all sidewall pores due to plasma etch and ash. For future technology, smaller pore size of porous Si-based low-k (=&lt; 50A) will be preferential for dense low-k like trench sidewall to avoid metal barrier integrity due to coverage problems from sidewall pores.

Reduction of the hydrogen degradation in SrBi2(Ta1−xNbx)2O9 by TiN barrier metal

The use of ferroelectric SrBi2(Ta1−xNbx)2O9 (SBTN) as a mainstream form of nonvolatile memory requires that the degradation of its electrical qualities that is caused by annealing in a hydrogen atmosphere be reduced. Titanium nitride (TiN) is a candidate for use as a barrier-metal layer against hydrogen diffusion. The relationship between the degradation in the qualities of SBTN and the quality of the TiN barrier metal has been investigated. TiN when sputtered onto SBTN capacitors creates a good barrier under all sputtering conditions, and maintains the electrical characteristics of the SBTN through annealing in an atmosphere of H2. Higher density TiN films provide more effective protection. The characteristics of the degraded capacitor were investigated in terms of its current-voltage characteristic. Remanent polarization can be recovered from, at least partially, by applying a series of bipolar pulses. This rejuvenation of the electrical qualities indicates that degradation arises from a combination of electrical and structural faults.

Abrasive‐Free Polishing for Copper Damascene Interconnection

A complete abrasive‐free process for fabricating copper damascene interconnection has been developed. The process is a combination of newly developed abrasive‐free polishing (AFP) of Cu and dry etching of a barrier metal layer. A new aqueous chemical polishing solution and a polyurethane polishing pad produce complete stop‐on‐barrier characteristics of Cu polishing. The AFP provides a very clean, scratch‐free, anticorrosive polished surface, and the total depth of erosion and dishing is reduced to less than one fifth of that produced by conventional slurries, even after 100% overpolishing. The barrier metal is successfully dry etched by using gas at a high selectivity ratio (more than 10) of barrier metal to . It was found that the developed AFP significantly reduces both Cu line resistance and its deviation. Moreover, AFP can also contribute to cost reduction of chemical mechanical polishing and help solve environmental problems related to waste slurries. © 2000 The Electrochemical Society. All rights reserved.

Development of Evaluation Method for Interface Strength Between Thin Films and its Application on Delamination of Cu/TaN in an Advanced LSI.

This paper aims to develop a method for evaluating interface strength of thin films on a substrate of LSI chip. Although several methods have been proposed, plastic deformation and fracture of thin metal film bring ambiguity on the interface strength evaluated by the methods in use. In this study, a sandwich specimen, where the deformation of thin films is tightly constraint by substrate and steel bar, is proposed for preventing the plastic strain and the fracture. The validity is examined by experiments for the interface between copper conductor film (thickness: 300nm) and TaN barrier metal layer (thickness: 50nm) in an advanced LSI. The delamination crack initiates from the free edge of interface where the tensile singular stress field, δ=Kfγ-λ (δ: stress and γ: distance from the edge), dominates. The criterion for the crack initiation is successfully evaluated as λ=0.08 and Kf=9MPa·mλ by the results of the proposed experiment and the boundary element analysis.There is little fluctuation of strength among the experiments.