Bang-bang Clock And Data Recovery Research Articles

A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique

This paper reports a reference-less frequency-detector-less single-loop bang-bang clock and data recovery (BBCDR) circuit featuring wide frequency acquisition. We use a current-starved ring oscillator controlled by a 5-bit resistive digital-to-analog converter to maintain quarter-rate operation, supporting a capture range of 110.4%. By the virtue of a deliberate-current-mismatch charge pump pair, we form the single-sided capture scheme in the frequency detection characteristic, eliminating the power-hungry circuits in the high-speed clock and data paths. Employing a hybrid control circuit, the proposed BBCDR automates frequency acquisition and phase tracking in the overall 32 bands. Prototyped in a 65-nm CMOS, the BBCDR covers a wide data rate from 10.8 to 37.4 Gb/s, achieving an acquisition speed of 4.63 (Gb/s)/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula> s and an energy efficiency of 1.3 pJ/bit.

A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS

This article reports a half-rate single-loop bang-bang clock and data recovery (BBCDR) circuit without the need of reference and frequency detector (FD). Specifically, we propose a deliberate-current-mismatch charge-pump pair to enable fast and robust frequency acquisition without identifying the frequency error polarity. This technique eliminates the need for a complex high-speed data or clock path during the frequency acquisition, resulting in significant power savings. Prototyped in 28-nm CMOS, the BBCDR circuit automatically tracks a four-level pulse-amplitude modulation (PAM-4) input between 47.6 and 58.8 Gb/s. The core area is 0.056 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Both the achieved energy efficiency (0.22–0.25 pJ/bit) and the acquisition speed [9.8 (Gb/s)/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> ] compare favorably with the state of the art.

A 0.0285-mm2 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS

This article reports a single-loop full-rate bang-bang clock and data recovery (BBCDR) circuit supporting a four-level pulse amplitude modulation (PAM-4) pattern. We eliminate both the reference and the separate frequency detector (FD) by deliberately adding two fixed strobe points in the bang-bang phase detector (BBPD) curve via a clock-selection scheme. As such, we can achieve a wide frequency-capture range in a single-sided FD polarity. The BBPD also incorporates a hybrid control circuit to automate the frequency acquisition over a wide frequency range. Prototyped in a 28-nm CMOS, the proposed BBCDR occupies a tiny area of 0.0285 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and exhibits a 23-to-29-Gb/s capture range. The acquisition speed [8.2 Gb/s/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> ] and energy efficiency (0.68 pJ/bit) compare favorably with the state of the art.

Equal-slope baud-rate CDR algorithm with optimized eye opening

A novel equal-slope baud rate clock and data recovery (CDR) algorithm is proposed. By positioning the locked point on pulse response where pre-cursor slope and main-cursor slope are equal, an optimized eye-opening is achieved with enhanced eye height, eye width and timing margin. The algorithm is realized in high-speed wireline receiver by finding the sampling position with maximum probability over an adaptive reference voltage when adjacent two data are opposite, with a double transition density over conventional Mueller-Muller (MM) algorithm. With no need for extra power-consuming or timing-critical circuits, this algorithm is readily integrated into prevalent decision feedback equalization (DFE). Simulation shows more than 18.0%, 14.4% and 56.1% improvement in recovered eye height, eye width and time margin, respectively, over its MM counterpart with >10 ​dB channel loss@14 ​GHz. Clear eye improvement could also be seen with respect to classical bang-bang CDR. Moreover, equal-slope CDR demonstrates significant locked point stability against system noise thanks to alienation from nearly-flat region.

A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS

This paper reports a half-rate bang-bang clock and data recovery (BBCDR) circuit supporting the trimodal (NRZ/PAM-4/PAM-8) operation. The observation of their crossover- points distribution at the transitions introduces the single-loop phase tracking technique. In addition, low-power techniques at both the architecture and circuit levels are employed to greatly improve the overall energy efficiency and multiply data throughput by increasing the number of levels on the magnitude. Fabricated in 28-nm CMOS, our BBCDR prototype scores a 0.29/0.17/0.14 pJ/bit efficiency at 14.4/28.8/43.2 Gb/s under NRZ/PAM-4/PAM-8 modes, respectively. The jitter is <; 0.53 ps (integrated from 100 Hz to 1 GHz) with approximately-equivalent constant loop bandwidth, and we achieve at least 1-UIpp jitter tolerance up to 10 MHz for all the three modes.

Analysis and Verification of Jitter in Bang-Bang Clock and Data Recovery Circuit With a Second-Order Loop Filter

This paper provides an in-depth analysis of the third-order bang-bang clock and data recovery (BBCDR) circuit, which accurately predicts its operating characteristics, namely, the jitter transfer function (JTF), the jitter tolerance (JTOL), and the jitter generation (JGEN). By formulating the time-domain waveforms, we introduce a characterizing method and also derive the closed-form equations and their simplified versions under specific conditions, which are related with the second-order loop filter (LF). Our framework is consistent with the conclusions of the prior works. Also, we discuss through the time-domain behavior, the sinking area of the JTOL and other specific phenomenon appearing in the third-order BBCDR loop. We verify all above prediction by system-level simulations with the MATLAB/simulink model.

A Low-Pass Filter Bandwidth Adaptation Technique for Phase Interpolators

This paper presents a technique to automatically adapt the bandwidth of the low-pass filter (LPF) of the phase interpolator (PI) used in bang-bang clock and data recovery (CDR) circuits. A technique for introducing the reference nonlinearity in the presence of PI’s nonlinearity is presented. This reference is used for LPF bandwidth adaptation. A mathematical model for the PI nonlinearity and introduction of reference nonlinearity is proposed. Using this model, analysis and design of the proposed bandwidth adaptation are done. The technique is verified by simulations and Si-measurements using a full-rate bang-bang CDR, which is fabricated in 180-nm CMOS technology. The PI occupies an area of 0.014 mm2 and consumes 1.1 mA for 1-GHz PI clock frequency while working on 1.8-V supply.

Half baud‐rate, low BER PAM‐4 CDR based on SS‐MMSE algorithm

A hardware-efficient four-level pulse amplitude modulation (PAM-4) clock and data recovery (CDR) circuit for high speed serial links is proposed, following a sign-sign minimum mean square error (SS-MMSE) algorithm. Using a specially designed continuous-sampling slope detector and a dual-stage digital filter, the proposed SS-MMSE CDR can align the clock phase well with the maximum vertical eye opening, as opposed to the conventional Bang-Bang CDR which only finds the midpoint of a symbol, yet requiring extra clock phases or running at higher frequency. Simulation results confirm superior performance and implementation efficiency of this proposed SS-MMSE PAM-4 CDR over the Bang-Bang design.

An 8–11 Gb/s Reference-Less Bang-Bang CDR Enabled by “Phase Reset”

This paper embeds a “phase-reset” scheme into a bang-bang clock and data recovery (CDR) to periodically realign the clock phase to the data rising edge using a gated-VCO. This reduces both the CDR lock time and bit errors during pull-in, while increasing the CDR capture range. The CDR is fabricated in 65-nm CMOS, operates at 8-11 Gb/s, and demonstrates a 9 × increase in capture range. The CDR consumes 84 mW during lock, and 48 mW in steady state.

A novel approach to analysis and design of bang-bang CDR circuits

Purpose – Bang-bang clock and data recovery (BBCDR) circuits are hard nonlinear systems due to the nonlinearity introduced by the binary phase detector (BPD). The specification of the CDR frequency response is determined by jitter tolerance and jitter transfer. In this paper, jitter transfer and jitter tolerance of the BBCDR are characterized. The paper aims to discuss these issues. Design/methodology/approach – The presented method is general enough to be used for designing the BBCDR loop parameters to meet SONET jitter transfer requirements (loop bandwidth and jitter peaking). Findings – In this paper, jitter transfer and jitter tolerance of the BBCDR are characterized by formulating the time domain waveforms. As a result, a new equation is presented to obtain angular frequency. Also, the jitter tolerance is expressed in closed form as a function of loop parameters. The validity of the resulted equations is verified through HSPICE simulations using TSMC 0.18-μm CMOS process. Simulation results show that good conformance between analytical equations and simulation results. Originality/value – The proposed approach offers two advantages compared to conventional designing methods. First, this approach does not consider any value restriction to the capacitor. Second, a new condition has been presented to guarantee that the value of jitter peaking is approximately zero. The presented method is general enough to be used for designing the BBCDR.

Nonlinear Analysis of BBCDR Jitter Generation Using VOLTERRA Series

Bang-bang clock and data recovery (BBCDR) circuits are severely nonlinear systems as a result of the binary phase detector's nonlinear behavior. The characteristic of the bang-bang phase detectors follows ideally the sign function, but in practice, it exhibits a finite slope across a narrow range of the input phase difference. In this brief, by considering an approximated practical model for the phase detector, the nonlinear differential equation of the system is obtained which shows that the BBCDR is a nonlinear system with memory and VOLTERRA series expansion is useful for such systems. As a result, the jitter generation of voltage-controlled-oscillator phase noise in BBCDR is specified. Behavioral simulation is used to validate the analytical results. The results show a good agreement between analytical equations and simulation results.

Modeling of Jitter in Bang-Bang CDR With Fourier Series Analysis

Bang-bang clock and data recovery (BBCDR) circuits are hard nonlinear systems due to the nonlinearity introduced by the binary phase detector (BPD). In this paper, jitter transfer and jitter tolerance of the second-order BBCDR are characterized by the Fourier series analysis and formulating the time domain waveforms. As a result, a new equation is presented to obtain corner frequency. Also, the jitter tolerance is expressed in a closed form as a function of loop parameters. The presented method is general enough to be used for designing the BBCDR. System level simulation is used to validate the analytical results with particular emphasis on jitter transfer and tolerance characteristics. The experiments all show excellent conformance between analytical equations and simulation results.

Application of Kalman Gain for Minimum Mean-Squared Phase-Error Bound in Bang-Bang CDRs

This paper presents the minimum bound of the mean-squared phase-error of a bang-bang (BB) clock-and-data recovery (CDR) circuit under the condition of random phase tracking. An analogy between the Kalman filter and a linearized BB CDR is utilized for the derivation. The effects of demultiplexing, loop latency, and granular jitter are considered in the analysis to reflect reality. The validity of the theoretical analysis is supported by behavioral time domain simulation results.

Modeling and Design of Multilevel Bang&amp;#x2013;Bang CDRs in the Presence of ISI and Noise

Multilevel clock-and-data recovery (CDR) systems are analyzed, modeled, and designed. A stochastic analysis provides probability density functions that are used to estimate the effect of intersymbol interference (ISI) and additive white noise on the characteristics of the phase detector (PD) in the CDR. A slope detector based novel multilevel bang-bang CDR architecture is proposed and modeled using the stochastic analysis and its performance compared with a typical multilevel Alexander PD-based CDR for equal-loop bandwidths. The rms jitter of the CDRs are predicted using a linear jitter model and a Markov chain and verified using behavioral simulations. Jitter tolerance simulations are also employed to compare the two CDRs. Both analytical calculations and behavioral simulations predict that at equal-loop bandwidths, the proposed architecture is superior to the Alexander type CDR at large ISI and low signal-to-noise ratios.

A 25-Gb/s CDR in 90-nm CMOS for High-Density Interconnects

This paper presents a clock-and-data recovery (CDR) for pseudo-synchronous high-density link applications. The CDR is a first-order bang-bang (BB) topology implemented in a standard CMOS process and consists of a phase interpolator, a linear half-rate phase detector, an analog filter followed by a limiter and a digital loop filter operating at a reduced clock rate. A detailed BB CDR analysis derives the maximum tracking range, slew-rate limited jitter tolerance and maximum loop delay. The circuit is optimized for high speed as well as low area and power consumption. The CDR operates from 8-28 Gb/s at a BER of <10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> and tracks frequency deviations between the incoming data and the reference clock of up to plusmn122 ppm. The sinusoidal jitter tolerance is >0.35UI <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> for jitter frequencies les100 MHz and the total timing jitter of the recovered half-rate output data amounts to 0.22 UIpp at a BER=10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> . The core CDR circuit occupies a chip area of 0.07 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 98 mW from a 1.1-V supply

A Digital Clock and Data Recovery Architecture for Multi-Gigabit/s Binary Links

In this tutorial paper, we present a general architecture for digital clock and data recovery (CDR) for high-speed binary links. The architecture is based on replacing the analog loop filter and voltage-controlled oscillator (VCO) in a typical analog phase-locked loop (PLL)-based CDR with digital components. We provide a linearized analysis of the bang-bang phase detector and CDR loop including the effects of decimation and self-noise. Additionally, we provide measured results from an implementation of the digital CDR system which are directly comparable to the linearized analysis, plus measurements of the limit cycle behavior which arises in these loops when incoming jitter is small. Finally, the relative advantages of analog and digital implementations of the CDR for high-speed binary links is considered