An 8–11 Gb/s Reference-Less Bang-Bang CDR Enabled by “Phase Reset”

Abstract

This paper embeds a “phase-reset” scheme into a bang-bang clock and data recovery (CDR) to periodically realign the clock phase to the data rising edge using a gated-VCO. This reduces both the CDR lock time and bit errors during pull-in, while increasing the CDR capture range. The CDR is fabricated in 65-nm CMOS, operates at 8-11 Gb/s, and demonstrates a 9 × increase in capture range. The CDR consumes 84 mW during lock, and 48 mW in steady state.