Bandwidth Mismatch Research Articles

Mismatches analysis based on channel response and an amplitude correction method for time interleaved photonic analog-to-digital converters.

A channel mismatch model for time-interleaved photonic analog-to-digital converters is built by decomposing both optical time division multiplexing channels and the wavelength division multiplexing channels into time channels with uniform and equal-amplitude sampling clock. Based on the model, the influence of power and timing mismatch of optical sampling pulse trains, optical sampling pulse temporal shape mismatches, photodetection bandwidth mismatches on the sampling results are analyzed theoretically. Depending on the found relationship between unmodulated components and modulated components, an effective online amplitude mismatch correction method applicable to wideband signals is proposed. The theoretical results are verified on a 4-channel TIPADC system. The proposed amplitude mismatch correction method can suppress the spurs caused by unmodulated components mismatch and modulated components mismatch by ~50 dB and ~30 dB for a two-tone signal, respectively.

Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters

This article reviews design challenges for low-power CMOS high-speed analog-to-digital converters (ADCs). Basic ADC converter architectures (flash ADCs, interpolating and folding ADCs, subranging and two-step ADCs, pipelined ADCs, successive approximation ADCs) are described with particular focus on their suitability for the construction of power-efficient hybrid ADCs. The overview includes discussions of channel offsets and gain mismatches, timing skews, channel bandwidth mismatches, and other considerations for low-power hybrid ADC design. As an example, a hybrid ADC architecture is introduced for applications requiring 1 GS/s with 6–8 bit resolution and power consumption below 11 mW. The hybrid ADC was fabricated in 130-nm CMOS technology, and has a subranging architecture with a 3-bit flash ADC as a first stage, and a 5-bit four-channel time-interleaved comparator-based asynchronous binary search (CABS) ADC as a second stage. Testing considerations and chip measurements results are summarized to demonstrate its low-power characteristics.

Study on the effects of distortions and common‐mode noise in high‐speed PAM‐4 systems

A study of different distortions in high-speed differential PAM-4 signals, including the linear distortions, i.e. amplitude mismatch, channel skew and bandwidth mismatch, and the non-linear distortion, i.e. the mismatch between rising and falling edges is presented. It is observed that only the non-linear distortion introduces a large common-mode (CM) noise at the double Nyquist frequency, which causes electromagnetic interference (EMI) in high-speed serial links. At last, Monte-Carlo simulations are performed to investigate the impact of signal distortions on the EMI-related CM noise.

A 5-GS/s 10-b 76-mW Time-Interleaved SAR ADC in 28 nm CMOS

This paper presents a 5-GS/s 12-way 10-b time-interleaved successive approximation register (SAR) ADC for direct sampling receivers. Proper signal and clock distribution along the multiple channels are utilized to mitigate interchannel bandwidth and timing mismatches. A digitally assisted calibration is introduced to remove the interchannel offset, gain, and timing mismatch. The T-type bootstrapped sampling switches minimize the interchannel crosstalk among top-plate sampling SAR channels and the signal-dependent leakage current during SAR conversion cycles. The power efficiency of this ADC is significantly improved by many design techniques. The merged capacitor switching algorithm leads to high switching efficiency and a smaller area. The modified reference voltage scheme optimizes input common-mode voltage of the comparators. The optimal subradix-2 capacitive DAC results in low-power reference buffers and higher conversion speed. This ADC achieves 49-dB SNR, 52-dB THD, and 42-dB SNDR up to Nyquist frequency at 5 GS/s, consumes 76 mW from 1 V supply, and occupies 0.57 mm $^{{ {2}}}$ in 28 nm CMOS technology. The implemented architecture also demonstrates high scalability to advanced CMOS technology nodes and has even higher power efficiency potential.

A 1.2-GS/s 8-bit Two-Step SAR ADC in 65-nm CMOS With Passive Residue Transfer

A high-speed 2b–1b/cycle two-step successive-approximation-register analog-to-digital converter (ADC) exploiting the passive residue transfer technique is reported. The removal of the residue amplifier results in savings in the time and power consumed by the residue transfer process. The kT/C noise and potential bandwidth mismatch associated with the passive residue transfer are analyzed and also verified by circuit simulations. The use of the 2b–1b/cycle hybrid conversion scheme with an appropriate resolution partition further enhances the conversion speed. Fabricated in a 65-nm CMOS process, the prototype ADC measured a signal-to-noise plus distortion ratio of 43.7 dB and a spurious-free dynamic range of 58.1 dB for a near-Nyquist input. The total power consumption of the ADC is 5 mW and the achieved figure of merit is 35 fJ/conversion-step, all measured at a sample rate of 1.2 GS/s.

A 12-bit 200MS/s pipeline ADC with 91 mW power and 66 dB SNDR

A 12-bit 200MS/s pipeline analog-to-digital converter (ADC) with sample-and-hold amplifier (SHA) is proposed in this paper. An innovative timing control technology is applied to the SHA in order to eliminate its nonlinear kickback, while the SHA eliminates bandwidth and timing mismatches between the input networks of the flash (sub-ADC) and of the multiplying DAC (MDAC) in the first stage, to improve the analog input bandwidth and to meet the requirements of a high-IF sampling ADC. A novel full complementary op-amp is utilized to reduce the overall power consumption of the ADC, which makes the power consumption of the SHA and of the first stage less than 20mW. A new fully differential reference buffer and a clock receiver with duty-cycle stabilizer (DCS) are applied in the prototype ADC. The jitter of the clock receiver is less than 150 fs to avoid the SNR degradation. The ADC is implemented in 0.18µm CMOS process and consumes 91mW from a 1.8V supply. The ADC achieves an SNDR of 66.10dB and an SFDR of 84.45dB with 10MHz input signal, while maintaining an SNDR >65dB and SFDR >80dB up in the entire Nyquist band. Its input signal frequency is up to 500MHz.

A Scalable Bandwidth Mismatch Calibration Technique for Time-Interleaved ADCs

This paper presents a foreground calibration method for both a sampler and a track-and-hold (T/H) buffer bandwidth mismatch in highly time-interleaved analog-to-digital converters (TI-ADCs). The T/H buffer bandwidth mismatch stems from the length difference of interconnect lines between the buffer and the channel ADC, while the sampler bandwidth mismatch arises from the mismatch in a switch and a sampling capacitor. To address both mismatches along with other mismatches residing in TI-ADCs, this papers utilizes least-squares (LS) minimization technique in order to extract mismatch parameters while injecting a sinewave at two distinct frequencies. Programmable capacitor arrays (PCAs) are used to tune the bandwidth of sampler, and correcting buffer bandwidth mismatch is performed in digital-domain. The method presented here is scalable to arbitrary number of interleaved paths, and can easily be combined with existing calibration methods for gain, offset, and timing-skew mismatches. Numerical experiment via Monte-Carlo simulations demonstrates significant performance improvement in the spurious-free dynamic range (SFDR) from 38 dB to 75 dB for a 32-channel time-interleaved ADC model that includes all major mismatches.

2D-to-3D conversion based hybrid frame discard method for 3D IPTV systems

One of the main limitations for 3D streaming services on IPTV is network bandwidth mismatch due to the large size of 3D video traffic. It causes fatal decoding errors and mosaic-like damage. This paper presents a hybrid frame discard method to address the problem. The main idea of the proposed method is combining the selective frame discard methodology with 2D-to-3D conversion technique, which enables efficient utilization of the network bandwidth. In the proposed method, the frames to be discarded are selected after consideration of the support of 2D-to-3D conversion, the network bandwidth, and the inter-frame dependency relationship within a group of pictures (GOPs). The experiment results demonstrate that the proposed method enhances the media quality of 3D video streaming even in bad network conditions. The proposed method is expected to be practically utilized in 3D IPTV system.

Analog Assisted Multichannel Digital Postcorrection for Time-Interleaved ADCs

This brief introduces a new digital postcorrection technique for calibrating time-interleaved analog-to-digital converters (ADCs). It utilizes one additional sub-ADC to resolve the performance degradation problem near the Nyquist rate that occurred in the conventional multichannel filtering approach. Time skew, gain, offset, and bandwidth mismatches as well as the sub-ADC nonlinearities are all included in the proposed model. One group of coefficients extracted in foreground can be applied to any input frequencies in normal operation. An additional analog subcircuit path is required, but the digital part of the implementation becomes much simpler, which ensures that the overall system complexity does not increase. Furthermore, the digital correction structure can reuse the hardware units in a time-multiplexing manner for further power and resource savings. A 12-b four-channel 1-GS/s ADC is used to demonstrate the performance of the proposed postcorrection.

Zero-Area Single-Photon Pulses.

Broadband single photons are usually considered not to couple efficiently to atomic gases because of the large mismatch in bandwidth. Contrary to this intuitive picture, here we demonstrate that the interaction of ultrashort single photons with a dense resonant atomic sample deeply modifies the temporal shape of their wave packet mode without degrading their nonclassical character, and effectively generates zero-area single-photon pulses. This is a clear signature of strong transient coupling between single broadband (THz-level) light quanta and atoms, with intriguing fundamental implications and possible new applications to the storage of quantum information.

A background fast convergence algorithm for timing skew in time-interleaved ADCs

Time-interleaved analog-to-digital converters (TI ADCs) suffer offset mismatch, gain mismatch, bandwidth mismatch and timing skew, of which timing skew degrades the performance most severely. In this paper, a background fast convergence calibration algorithm for timing skew is proposed. With known the range of input frequency, the algorithm employs the statistical property of the wrong digital outputs to estimate the sign of the timing skew. Then a correction module based on polynomial interpolation starts to compensate the wrong outputs. This algorithm has some merits of simplicity, fast convergence rate and feasible to implement. Behavioral simulation of an 8-bit 8-channel 3.2GS/s TI ADC reveals that with an input frequency of 0–1.4GHz, this algorithm is effective to improve the signal-to-noise distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of the TI ADC.

Adaptive and joint blind calibration of gain, time‐skew and bandwidth mismatch errors in time‐interleaved ADCs

A new blind calibration scheme for M time-interleaved analogue-to-digital converters (ADCs), which models gain, time-skew and bandwidth mismatches as components of a transfer function mismatch, is proposed. Numerical results on the emerging generation of WiFI IEEE 802.11.ac with 12-bit ADCs show the effectiveness of the method.

Subsampling Models of Bandwidth Mismatch for Time-Interleaved Converter Calibration

Bandwidth mismatch is one of the mechanisms that reduce linearity in time-interleaved analog-to-digital converters (TI-ADCs). Models of bandwidth mismatch have been already proposed in the literature: this brief extends them to subsampling signals, validates them against circuit-level simulations, and investigates their effect on linearity in subsampling applications. The effectiveness of two previously published calibration algorithms for the correction of bandwidth mismatch is shown. The proposed models can thus be used to simulate subsampling TI-ADCs and their calibration algorithms.

A 65 nm CMOS Power Amplifier With Peak PAE above 18.9% From 57 to 66 GHz Using Synthesized Transformer-Based Matching Network

Maintaining good power performance in a large bandwidth continues to challenge the design of millimeter-wave (mm-wave) power amplifiers (PAs), including mm-wave PAs with transformer-based matching networks (TMNs). With a TMN synthesizing method which is proposed based on the derived matching equations of TMN, this challenge is addressed in this paper for wideband mm-wave PAs by designing both inter-stage matching networks and output matching network with small mismatch in the entire operating bandwidth. A 60 GHz PA with synthesized TMNs is designed in a 65 nm bulk CMOS technology, achieving smaller degradation of power performance in the 9 GHz bandwidth compared to reported works in more advanced CMOS technologies. From 57 to 66 GHz, the PA is measured with saturated output power $({\rm P}_{\rm SAT})$ of 13.94 to 14.35 dBm, ${\rm P}_{1{\rm dB}}$ of 10.81 to 11.68 dBm, and peak power added efficiency (PAE) of 18.9% to 21.1%. The PA is capable of delivering 16QAM modulated signal with output power larger than 10.8 dBm and PAE higher than 10.1% in all the 4 channels of 802.11ad when EVM is 8.91%.

On Robustness of Hybrid Digital/Analog Source-Channel Coding With Bandwidth Mismatch

For transmission of memoryless Gaussian sources over channels with additive white Gaussian noise, the tradeoff between the distortion when the channel quality is good versus bad is investigated under the constraint that the distortion is optimal when the channel has the targeted median quality. The problem was proposed by Tian and Shamai, who subsequently proved remarkable achievability results for bandwidth expansion ratios $\kappa $ , which are integers or unit fractions, i.e., $\kappa =2,3,4,\ldots $ or $\kappa =1/2,1/3,1/4,\ldots $ Their result is extended here to all $\kappa \geq 2$ and $\kappa \leq 1/2$ by generalizing the hybrid digital/analog (HDA) scheme of Wilson et al. to the case of bandwidth mismatch. Finally, novel schemes are proposed for $1/2\leq \kappa and $1 achieving nontrivial tradeoffs outperforming all known schemes. These latter schemes rely on another extension of the HDA scheme by Wilson et al. , namely, the relaxation of the independence of source and channel input sequences.

A General Digital Predistortion Architecture Using Constrained Feedback Bandwidth for Wideband Power Amplifiers

Digital predistortion (DPD) is one of the most effective techniques to mitigate the distortions caused by power amplifier (PA) nonlinearity and memory effects. As the input signal bandwidth increases, the required bandwidth on the DPD feedback channel becomes even larger, i.e., normally five times the signal bandwidth. However, the DPD feedback bandwidth is often restricted by the nonideal electronic components, e.g., the anti-aliasing filter and associated circuits, which therefore introduce bandwidth mismatch between the PA model basis functions and the feedback signal, and thus degrade the linearization performances of the DPD. This paper presents a general DPD architecture for wideband PA systems with constrained feedback bandwidth. By using linear operations to cancel the bandwidth mismatch between the proposed model and the PA feedback signal, the full-band PA model parameters can be estimated with bandwidth-limited observations. This estimated PA model is subsequently used with the PA input signal to extract the DPD function by applying the direct learning algorithms. The proposed DPD architecture reduces the feedback bandwidth to less than two times that of the input signal, while it maintains its linearization performance, as in the full-band case. Experiments are performed on the 20- and 100-MHz long-term evolution advanced signals to demonstrate the effectiveness of the proposed PA behavior modeling and DPD linearization performances with limited feedback bandwidth.

Comprehensive Background Calibration of Time-Interleaved Analog-to-Digital Converters

A dynamic path-mismatch calibration operating on direct derivative information (DDI) augments the reference-path equalization technique of that treats static mismatch errors in time-interleaved (TI) analog-to-digital converters (ADC). The approach results in a comprehensive background calibration of interleaved ADC arrays suitable for digitizing wideband inputs. The DDI of the analog input is produced by a passive high-pass filter (HPF) followed by a zero-crossing comparator, and subsequently utilized in the process to extract the dynamic mismatch profiles of the TI conversion paths, i.e., timing skew, bandwidth mismatch, etc. A zero-forcing algorithm drives the adaptive tuning procedures of the converter front-end circuits to eliminate the mismatch errors at source. The non-idealities of the DDI circuitry and their impact on the calibration performance are discussed. Behavioral simulation of an 8-bit, 20-GS/s TI-ADC reveals that signal-to-noise plus distortion ratio (SNDR) and spurious-free dynamic range (SFDR) over 47 dB and 70 dB, respectively, can be routinely obtained for single-tone inputs from DC to Nyquist after calibration, demonstrating the efficacy of the proposed technique.

Background analog and mixed signal calibration system for time-interleaved ADC

In this work, a novel background calibration technique for time-interleaved analog-to-digital converters (ADCs) is proposed. The offset, gain, time skew and bandwidth mismatches are considered and analyzed in detail, highlighting the efficiency of the proposed calibration method. The calibration system is an analog mixed one where the error detection is performed digitally by three detectors: offset detector, amplitude detector and phase detector. The correction is performed in both the analog and the digital domains. We have proposed a calibration sequence that allows us to distinguish between the different errors, resulting in high accuracy detection and correction phases. The efficiency and the accuracy of the calibration technique are verified through MATLAB® and VHDL-AMS simulations.

Design of frequency‐interleaved ADC with mismatch compensation

A frequency-interleaving-based multichannel analogue-to-digitial converter (ADC) with mismatch compensation is presented, which is immune from the time skew problem that exist in the time-interleaved ADC. The channel mismatches, such as bandwidth mismatch, gain mismatch, offset mismatch and filter bank mismatch, are addressed and modelled in the reconstruction optimisation. A prototype of a four-channel 1 GS/s 12 bit frequency-interleaved ADC (FI-ADC) is designed to demonstrate the mismatch compensation. Simulation results show that the mismatches in the FI-ADC can be compensated effectively.

A 72 dB DR, CT ΔΣ Modulator Using Digitally Estimated, Auxiliary DAC Linearization Achieving 88 fJ/conv-step in a 25 MHz BW

This paper presents a single loop, third order continuous time ΔΣ modulator with an internal 4 bit quantizer sampled at 500 MHz with only an oversampling ratio of 10. Since multi-bit operation commonly suffers from DAC non-linearities, and dynamic element matching is ineffective at low oversampling, an alternative auxiliary DAC linearization is proposed for ΔΣ modulators. The unit element mismatches are digitally estimated based on a cross correlation of a binary test signal with the modulator output and represent the measured DNL of DAC1. The corresponding INL is calculated and stored in an 15×8 lookup-table which is applied to the 8 bit auxiliary DAC to linearize DAC1. Moreover, a design centering approach for amplifier finite gain bandwidth compensation within the loop filter is presented which allows for large bandwidth mismatch with negligible effect on loop filter stability. This results in a robust architecture over temperature, supply, and excess loop delay variations. The presented ΔΣ modulator achieves an SNDR of 67.5 dB, DR of 72 dB, and SFDR of 79 dB over a 25 MHz bandwidth and is implemented in a 1.2 V, 90 nm CMOS process. The modulator occupies an active area of 0.19 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and has a power consumption of 8.5 mW. It achieves a figure of merit of 88 fJ/conv-step which is one of the best published for multi-bit ΔΣ modulators.