Ball Grid Array Research Articles

Improving Reliability of Fan -Out Wafer Level Package Through Doping of Lead-Free Solder Balls

Embedded wafer level ball grid array (eWLB) or FO-WLP (Fan-out wafer-level packaging) is investigated as a package for MMICs (Monolithic Microwave Integrated Circuit) for automotive radar applications in the 77GHz range. Doping of Bi and/or Sb was applied to improve the resistance of lead-free SAC balls against thermal cycling stress. We have shown that by increasing the doping level the lifetime can be increased and determined the maximum doping level before extrinsic failure modes dominate. It is well-known from the literature that doping of Bi and/or Sb improves the resistance of lead-free SAC balls against thermal cycling stress. It was shown that lifetime of FC-BGA package can be multiplied using Bi and/or Sb doping. The lifetime gain is achieved by reduced creepage of the hardened balls caused by the doping. This reduced creepage increases the risk of causing other failures than ball cracks in the eWLB package or the PCB during thermal cycling stress. We have tested robustness of 7x8,5 mm^2 eWLB packages against thermal cycling stress T = -40 to 125 °C using SAC-balls with different Bi-doping content from 0% to 2,5% Bi concentration. As could be expected the solder ball fatigue mode is delayed more and more increasing the Bi content. We found other failure modes than solder ball fatigue emerging at doping around 1%. The fatigue modes are shifted towards cupper lines on PCB or into the package. Cu line cracks can be overcome by switching the PCB layout from NSMD (non solder-mask defined) to SMD (solder-mask defined) solder pads. In general there is a lifetime penalty when switching from NSMD to SMD, but by avoiding the Cu line cracks this lifetime loss is overcompensated using SMD pads for optimum performance. As input for simulations we have characterized the doped solder material using specimens produced in glass columns. We have also tested the components on PCBs with different top layer laminate with different CTE and elastic modulus to assess the influence of the PCB properties on the lifetime. It is a trend in automotive radar systems to use stiffer laminates which are cheaper but have negative influence on component lifetime. Solder ball shear tests were also carried out to characterize the influence of ball doping on other board-level reliability beyond thermal cycling performance. As expected ball shear force is increased with increased doping level. At increased shear-force the shearing is still done through the solder ball and does not lead to different shear-mode. Finally drop-tests were done to check influence of doping on board-level reliability performance other than thermal-cycling performance.

Optimal Design of Thermal Cycling Reliability for Plastic Ball Grid Array Assembly Via Finite Element Method and Taguchi Method

Abstract A finite element simulation analysis model was developed for a plastic ball grid array (PBGA) assembly to analyze its behavior under thermal cyclic loading conditions. The stress distribution in the SAC305 solder joints at different locations within the array was investigated by using ANAND constitutive equations. Subsequently, the thermal fatigue life of the key solder joints was quantified. The study also examined the influence of the solder joint diameter, substrate thickness, solder joint height, printed circuit board (PCB) thickness, and mold compound height on solder joint stress. Optimization of assembly parameters was achieved through the application of the Taguchi method. An extensive analysis was conducted using different assembly parameter combinations, employing the L9(34) orthogonal array design to explore the thermal cycling effects. The computed average Von Mises stress Δσ for the critical thin-layer elements of solder joints located in hazardous positions within the assembly was notably affected by variations in the solder joint height, substrate thickness, solder joint diameter, and mold compound height. This impact ranked in descending order of significance as solder joint height, substrate thickness, solder joint diameter, and mold compound height. The optimal parameter combination determined was a solder joint height of 0.70 mm, a solder joint diameter of 0.85 mm, a substrate thickness of 0.51 mm, and a mold compound height of 1.12 mm. Implementing this optimized configuration led to a significant 4.07% reduction in average stress Δσ for the critical thin-layer elements within hazardous solder joints. Moreover, the extension of the thermal fatigue life was notably improved, achieving an impressive 51.72% increase.

CU Wirebond Technology in 16FFC High Performance Automotive Radar Processor with IR Drop Reduction Methodology

High performance automotive radar front-end processors normally use advanced semiconductor packaging such as Flip Chip, fan-in and fan-out wafer level Ball Grid Array (BGA) packages in order to provide superior performance in their applications. However, for a cost effective package in the competitive business market, wirebonded package can also provide similar uncompromised performance. Advanced Cu wirebond technology was evaluated on the 16FFc radar processor. However, the challenge of high voltage drop, also known as IR drop, in 16FFc technology has to be overcome. As wafer technology moves to smaller advanced nodes, the back-end-of-line (BEOL) metal thickness gets thinner, thus increasing the resistance per unit length. Another trend in semiconductor design has been a reduction in operating voltage, meaning that small changes in supply voltage may represent an increasing percentage of the digital swing and potentially lead to incorrect logic values. As current flows through a resistor, the high voltage drop could slow down the circuitry, impact the circuit timing and lead to functional failure. In order to reduce the IR drop in the radar processor when using Cu wirebond, a large quantity of intra-die wires was applied on the 16FFc silicon. IR drop simulation was performed on 3 layout conditions, 0%, 50% and 100% of the intra-die wires. Empirical data was also collected with actual Cu wirebonded samples. The fully populated intra-die wires reduced IR drop by 30%. To enable the reliable performance of the intra-die wires, Stand-off Stitch Bond (SSB) wirebond technology was introduced within the package. The development and reliability evaluation was conducted for Cu wirebonding on 16FFc automotive radar processor of 30mm2 die size in a 14mm x14mm 2-layer substrate BGA package. Wirebond recipe was developed based on detailed Design of Experiment to establish bonding parameters for both standard wires and the intra-die wires. Packages were tested per AEC Grade 1 and AEC Q006 qualifications requirements. All results from package reliability assessments passed with no abnormality. Board level temperature cycling reliability for the BGA package with the four depopulated corner solder balls was evaluated with results surpassing NXP requirement for AEC Grade 1. This paper will present the results and analysis from (1) IR drop simulation and empirical data collection, (2) wirebond development and reliability of standard and intra-die wires on 16FFc Silicon, and (3) board level reliability of a BGA package with four depopulated corner solder balls.

3D CT scan metrology for solder void formation analysis in ball grid array electronic chips

The miniaturization of silicon chips and the complexity of device functionality has driven the electronic packaging industry to find new methods to enhance the reliability of chips at a smaller size. Solutions such as Ball Grid Array (BGA) packages have contributed to the miniaturization of integrated circuits (ICs) and the reduction in their overall size. However, void formation in the solder joint is a weakness that can affect the robustness of the solder joint integrity, both mechanically and electrically. To detect these voids, metrology methods such as 3D Computed tomography (CT)-scan are used. 3D CT-scans can identify submicron-sized void defects in real-time during thermal tests, which can be utilized to help improve the quality control lines in the electronic chip manufacturing industries. In this paper, two types of BGA packages will be evaluated for solder joint properties. The prepared samples will be subject to high temperature stress conditions to assess the mechanism of void formation in solder joint. The prepared samples will be heated at 260 °C four times where the heating lasts 0, 5, 10, and 15 min, respectively. The prepared samples will be mounted on a PCB board and the results of the thermal stress tests will be analyzed using 3D X-ray CT scans. These 3D-CT scans used in tandem with a reconstruction and visualization software suite, will be utilized to observe changes such as void formation in the solder joint after each heating time. Unexpectedly, void size reduced between the first and second heat cycles on both samples but increased for the third and fourth heat cycles then.

Effectiveness of Critical-Strain-Based Methodology Considering Elastic Mode Vibration of Mechanical Housing of Electronics

A critical-strain-based methodology was proposed to overcome the theoretical limitations of Steinberg’s method, and its effectiveness was experimentally verified through fatigue tests of ball grid arrays, column grid arrays, and lead-type specimens on printed circuit boards (PCBs) with various boundary conditions. These verifications were performed only on PCB units with a single electronic package mounted. However, in actual industrial fields, electronics with various types of electronic packages mounted comprehensively are mainly applied to electronics combined in a mechanical housing structure. Therefore, the verification of the corresponding methodology for the above actual conditions is essential. This study aimed to validate the theoretical feasibility of the design technique under the condition that the elastic mode vibration of a mechanical housing structure acts complexly on PCBs. The proposed methodology was validated analytically and experimentally through a vibration test on a comprehensive PCB specimen with various types of electronic packages mounted on electronic mechanical housing structures.

Analytical equivalent circuit modeling and analysis of complex BGA for 3D silicon-interposer packaging

Through analyzing different cross-sections of the complex ball grid array (CBGA) sandwiched by silicon interposers, various distributed capacitances of the CBGA and the significance of the CBGA's coplanar capacitances are revealed. From the analyses, the composition of the CBGA's capacitance is found to have similarity with that of the coplanar waveguide's capacitance. Based on the electric-field coupling mechanism of the coplanar waveguide, geometrical analysis of the CBGA, and analysis of multiconductor transmission lines, analytical equations are derived to allow accurate modeling the equivalent circuit of the CBGA for 3D silicon-interposer packaging. The modeled equivalent circuit of the CBGA is validated with the full wave electromagnetic simulation, and it is demonstrated to have a good accuracy up to 40 GHz. Moreover, the CBGA structure can be further optimized for impedance matching with the guidance of the derived analytical equations.

Solder Flux Evolution for Heterogeneous Integration

Advanced packaging techniques continue to evolve within the semiconductor industry. Within advanced packaging, heterogeneous integration has become a solution for those wishing to integrate distinct and complex dies into smaller packages. Many application trends are emerging to meet the challenges of heterogeneous integration which are causing the assembly process to become more intricate, with these trends requiring soldering material technology, especially that of solder flux, to be up to date and cutting-edge. In this paper, three assembly processes that necessitate advanced solder flux will be discussed: flip-chip assembly, BGA ball-attach assembly, and assemblies which have advanced to necessitate fluxless component attach. First, flip-chip assembly methods will be discussed and how different assembly technologies, such as standard mass reflow, thermocompression bonding (TCB), and laser assisted bonding (LAB), require differently formulated fluxes. This paper will then discuss the ball grid array assembly process, first outlining common process steps which negatively affect the solderability of ball-grid array pads, such as flip-chip reflow and molding compound applications, then discuss advancements in ball-attach fluxes which help eliminate these extra process steps, or ‘prefluxing’ steps. Finally, this paper will then discuss assembly trends which have led to fluxless component attach, and will discuss materials designed for fluxless processes, such as formic acid reflow, and how these fluxless processes tie into flip-chip assembly.

Corrosion behavior and failure mechanism of ball grid array packages in fire smoke atmospheres

Ball grid array (BGA) packages is a common type of electronic packaging and a crucial component in electronic devices. However, its reliability is significantly compromised when exposed to fire smoke atmospheres, thereby reducing the overall reliability of electronic equipment. Therefore, the study of failure mechanisms of BGA packages in fire smoke environments is of paramount importance for the recovery and maintenance of electronic devices post-fire. In this study, we conducted fire smoke experiments and employed electrical performance measurements along with chemical characterization techniques to delve into the failure behaviors and mechanisms of BGA packages in different fire smoke atmosphere. The results reveal that nitrile-butadiene rubber and polycarbonate smoke do not affect the electrical conductivity of BGA packages. However, the accumulation of smoke particles and water between the interconnecting solder joints temporarily reduces the insulation performance. That is induced by the deposition of smoke particles and can be restored after cleaning. On the other hand, under polyvinyl chloride smoke, BGA packages experiences insulation failure and permanent open-circuit failure. This irreversible permanent open-circuit failure is caused by the interconnection of corrosion products in solder joints. Chemical characterization analysis results indicate that solder joints dissolve due to the galvanic corrosion mechanism, transforming the solder from a spherical shape into a rose-like structure. The corrosion products primarily consist of flake-like SnO and Sn3O(OH)2Cl2. This research contributes to a deeper understanding of the failure mechanisms of electronic devices in fire smoke and provides essential guidance for post-fire equipment maintenance.

Leadfree SnAgCu Solder Materials Characterization at High Strain Rates at Low Test Temperatures and Drop and Shock Simulation Using Input-G Method

Abstract Electronics will experience high and low working temperatures during operations, handling, and storage in severe environments applications such as download drilling, aircraft, and transportation. Temperatures in the vehicle underhood applications can range from −65 °C to +200 °C. Lead-free solder materials continue to evolve under varying thermal workloads. Material characteristics may deteriorate if operating conditions are harsh or heavy. Nonetheless, lead-free solders are susceptible to high strains, which can lead to electronic device failure. A better understanding of solder alloys is needed to ensure reliable operation in harsh environments. New doped solder alloys have recently been created by adding Ni, Co, Au, P, Ga, Cu, and Sb to SnAgCu (SAC) solder alloys to improve mechanical, thermal, and other qualities. SAC-Q has recently been made using Sn–Ag–Cu and the addition of Bi (SAC+Bi). It was discovered that adding dopants to SAC alloys may enhance mechanical characteristics and reduce aging damage. There is no published data on SAC solder alloys after prolonged storage at high strain rates and low functioning temperatures. The materials characterization of SAC (SAC105 and SAC-Q) solder after extended storage at low working temperatures (−65 °C–0 °C) and high strain rates (10–75 per sec) is investigated in this article. To characterize the material constitutive behavior, the Anand viscoplastic model was utilized to derive nine Anand parameters from recorded Tensile data. The generated nine Anand parameters were used to validate the Anand model's reliability. A strong correlation was established between experimental data and Anand's predicted data. The Anand parameters were used in a finite element framework to simulate drop events for a ball-grid array package on printed circuit board assembly to calculate hysteresis loop and plastic work density. The plastic work per shock event measures the damage progression of the solder interconnects. Thermal aging effects have been studied in terms of the hysteresis loop and the evolution of PWD.

Numerical Investigation of the Evolving Inelastic Deformation Path of a Solder Ball Joint under Various Loading Conditions

Solder joints of ball grid arrays (BGA) have been widely used to connect electronic components to printed circuit boards (PCBs) and are often subjected to mechanical stress. Several studies have been conducted on the mechanical reliability of solder joints. While these studies have been useful in the industry, detailed studies on how the inelastic deformation path of the solder ball joints evolves under specific loading conditions have not been sufficiently reported. This study aims to understand how the inelastic deformation path evolves when a solder joint is subjected to a constant external force by utilizing the theory of mechanics. It has also been found that the mechanical failure is strongly influenced by the evolution history of the deformation modes in materials. For this study, an elastoplastic constitutive model and a ductile fracture criterion were implemented into the vectorized user-defined material (VUMAT) subroutine of the ABAQUS program for finite element (FE) analysis. With the model, the evolution of the inelastic deformation path of a single solder ball under different loading conditions was numerically analyzed. Three loadings (shear, compression, and bending) were chosen as the basic loading conditions. In addition, combinations of the basic loadings resulted in three dual loadings and one complex loading. The simulation results showed that the shear and bending caused the fracture for both single and dual loadings, but when combined with compression, the fracture was suppressed. The results indicate that fracture is not solely determined by the magnitude of equivalent plastic strain but also by the evolution of inelastic deformation mode. This research offers an improved understanding of the significance of the inelastic deformation path and fracture.

Study of the effect of crystal orientation on the mechanical response and fatigue life of solder joints under thermal cycling by crystal plasticity

Electronic products are subjected to thermal cycling caused by power cycling in service processes. Owing to the difference in the coefficients of thermal expansion (CTEs) of solder joints and other packaging materials, solder joints suffer from thermomechanical fatigue, and cracks appear at their bonding interfaces. Solder joints are usually a single grain or three grains with Beachball morphology, and their composition is Sn-based Pb-free SAC305 (96.5Sn–3.0Ag–0.5Cu wt.%) solder, which exhibits obvious anisotropic mechanical behavior. This study investigated a thermal cycling simulation of Plastic Ball Grid Array (PBGA) packaging, in which the Anand model was used for solder joints, and the outermost solder joint was found to be a dangerous point. Sub-models were then established for this solder joint with several typical crystal orientations. The effect of crystal orientation under thermal cycling was simulated using thermomechanical crystal plasticity. When the c-axis of Sn crystal was perpendicular to the substrate, the deformation resistance was the largest, and the accumulation of equivalent plastic strain and strain energy dissipation was the slowest; hence, the fatigue life was the longest. As the angle between the c-axis and the substrate decreased, the deformation accumulated faster. When the c-axis was parallel to the substrate, the deformation of the solder joint was the fastest, and thus this joint was the first to fail and had the shortest fatigue life. In addition, the simulation of three grains indicated that orientations and their distributions had an influence on the shear strain accumulation of slip systems and fatigue life.

Bonding Property of Middle Temperature Sn-Ag-Cu Solder Ball Joint of Ball Grid Array Package

Alloying effects of Nickel and Bismuth in SAC solder to achieve mechanical and microstructural evolution were investigated by comparing three different chemical composition of solders. Sn-3.0Ag-0.5Cu (SAC305) is the most commonly used for Pb-free solder and solder balls are based on Sn-Ag-Cu alloy composition. Compositions of solder balls were Sn-3.0Ag-0.5Cu (SAC305), Sn-1.2Ag-0.5Cu-0.05Ni (SAC1205N) and Sn-Ag-Cu-Ni-Bi based solder (SACNB). Organic solderability preservative (OSP) surface finished substrate, ball grid array (BGA) package arranged by 300 ㎛ diameter solder ball and Type 4 solder paste were used. Solder ball shear test of the BGA package was conducted before the reflow soldering. Board level package bonding process was carried out by hot air reflow soldering. Void content of the BGA solder joint was investigated after soldering. The microstructure evolution before and after thermal cycle test (TCT) was observed using scanning eletron microscopy (SEM) and energy dispersive spectroscopy (EDS). After TCT, intermetallic compound (IMC) refinement and solid solution strengthening effects of Bi element addition were observed in the solder matrix, and also any segregation of Bi element was not founded. Based on these result, it was found that the solder joint reliability of the middle and low temperature solder joints was improved.

Deep learning and analytical study of void regional formation in flip-chip underfilling process

PurposeThis paper aims to study the relationship between the ball grid array (BGA) flip-chip underfilling process parameter and its void formation region.Design/methodology/approachA set of top-down scanning acoustic microscope images of BGA underfill is collected and void labelled. The labelled images are trained with a convolutional neural network model, and the performance is evaluated. The model is tested with new images, and the void area with its region is analysed with its dispensing parameter.FindingsAll findings were well-validated with reference to the past experimental results regarding dispensing parameters and their quantitative regional formation. As the BGA is non-uniform, 85% of the test samples have void(s) formed in the emptier region. Furthermore, the highest rating factor, valve dispensing pressure with a Gini index of 0.219 and U-type dispensing pattern set of parameters generally form a lower void percentage within the underfilling, although its consistency is difficult to maintain.Practical implicationsThis study enabled manufacturers to forecast the void regional formation from its filling parameters and array pattern. The filling pressure, dispensing pattern and BGA relations could provide qualitative insights to understand the void formation region in a flip-chip, enabling the prompt to formulate countermeasures to optimise voiding in a specific area in the underfill.Originality/valueThe void regional formation in a flip-chip underfilling process can be explained quantitatively with indicative parameters such as valve pressure, dispensing pattern and BGA arrangement.

Research on Processability and Transmission Performance of Low Temperature Co-Fired Ceramic Ball Grid Array Packaging Based on Electroless Plating Surface Modification for Microwave Transceiver Circuits.

A microwave transmitter/receiver using the low-temperature co-fired ceramic substrate and ball grid array packaging demonstrates superior properties, including high integration, miniaturization, and high electromagnetic shielding. However, it holds limitations of inadequate hermeticity (that is, gas or moist impermeability), high cost, and low reproducibility. In this work, we aim to overcome these difficulties by introducing a new packing technique. The packaging utilizes an electroless plated Ni/Pd/Au surface, resulting in a significant enhancement of the packaging hermeticity by orders of magnitude, approaching the level of <5 × 10-9 Pa·m3/s. Both Sn63Pb37 and Au80Sn20 solder alloys demonstrate exceptional solderability, attributed to Pd atoms diffusing to the Au layer during soldering at 310 °C. A reliability test of the packaging shows that the shear strength of the solder balls drops after thermal shocks but negligibly affects the hermeticity of the packaging. Furthermore, a meticulously designed internal vertical interconnect structure and I/O interconnections were engineered in the ball grid array packaging, showcasing excellent transmission characteristics within the 10-40 GHz frequency range while ensuring effective isolation between ports.

Equilibrium phase diagram design and structural optimization of SAC/Sn-Pb composite structure solder joint for preferable stress distribution

The Package-on-Package (PoP) technology is an efficient knowhow to increase the efficiency of electronic components, hence to secure the continuation of the validity of Moore's law. This novel form of packaging technology with bottom stackable narrow pitch Ball Grid Array (BGA) contributes to the integrity of the package. However, the high solder joint density introduces a great challenge on the packaging reliability. Therefore, more stringent requirements must be put forward for achieving the increased performance. That can be achieved by using composite solder joints. In this study, a novel composite SAC (Sn-3Ag-0.5Cu)/Sn-Pb (Sn37Pb) solder joint was designed for improving the stress distribution and its overall mechanical integrity. The formation process and a phase distribution of composite solder joint were investigated, indicating that the phase distribution mainly depends on the reflow temperature. The dissolution ratio of SAC into the composite solder at different temperatures was estimated by the phase diagram. The predicted values were consistent with the experimental results. A review of mechanical property test results, the best performance solder joint could be obtained at 200 °C for the dwell time of 60 s if the composite includes 10 wt% SnPb. The stress distribution of composite solder joint was analyzed by finite element simulation. By actively concentrating the stress in the middle area of the solder joint, the maximum stress in the composite solder reduced for up to 29% when compared to full SAC solder joint.

Investigation on the new reliability issues of PCB in 5G millimeter wave application

PurposeThe purpose of this paper is to illustrate the new technical demands and reliability challenges to printed circuit board (PCB) designs, materials and processes when the transmission frequency increases from Sub-6 GHz in previous generations to millimeter (mm) wave in fifth-generation (5G) communication technology.Design/methodology/approachThe approach involves theoretical analysis and actual case study by various characterization techniques, such as a stereo microscope, metallographic microscope, scanning electron microscope, energy dispersive spectroscopy, focused ion beam, high-frequency structure simulator, stripline resonator and mechanical test.FindingsTo meet PCB signal integrity demands in mm-wave frequency bands, the improving proposals on copper profile, resin system, reinforcement fabric, filler, electromagnetic interference-reducing design, transmission line as well as via layout, surface treatment, drilling, desmear, laminating and electroplating were discussed. And the failure causes and effects of typical reliability issues, including complex permittivity fluctuation at different frequencies or environments, weakening of peel strength, conductive anodic filament, crack on microvias, the effect of solder joint void on signal transmission performance and soldering anomalies at ball grid array location on high-speed PCBs, were demonstrated.Originality/valueThe PCB reliability problem is the leading factor to cause failures of PCB assemblies concluded from statistical results on the failure cases sent to our laboratory. The PCB reliability level is very essential to guarantee the reliability of the entire equipment. In this paper, the summarized technical demands and reliability issues that are rarely reported in existing articles were discussed systematically with new perspectives, which will be very critical to identify potential reliability risks for PCB in 5G mm-wave applications and implement targeted improvements.

Effect of gamma irradiation on microstructural evolution and mechanical properties of SnPb eutectic solder joints

Eutectic SnPb ball grid array (BGA) solder joints were exposed to 60Co source gamma irradiation at a dose rate of 1 Gy(Si)/s from 0, 50, 100, 150 and 200 h in air. The effects of gamma irradiation on the microstructure evolution and mechanical properties of the solder joints were investigated. After irradiation, β-Sn and Pb on the surface of the solder joint was oxidized to SnO2, PbO and PbO2, and an oxide layer covered with Cu oxide was formed on the surface of the solder joint. The formation process and mechanism of the oxide layer were analyzed. Sn and Pb depletion holes and Cu depletion areas appeared on the solder joint surfaces after various irradiation time. SnO2 nanocrystals and Sn wrinkles appeared in the FIB specimen after irradiation. After 200 h of irradiation, the melting temperature of the SnPb eutectic solder alloy decrease, and the shear force value of the solder joint first increase and then decrease.

Enhanced size effects on shear performance and fracture behavior of BGA structure micro-scale Cu/Sn–3.0Ag–0.5Cu/Cu joints at low temperatures

To assess the serving reliability of shrinking-sized solder joints in space electronics (especially cryogenic electronics), the effects of joint size on the shear performance of Cu/Sn–3.0Ag–0.5Cu/Cu joints with ball grid array (BGA) structure at different temperatures (25 to −125 °C) were investigated. As the joint size decreased, shear strength of the solder joint increased, showing prominent size effect, which was enhanced at low temperatures. Moreover, a ductile-to-brittle transition (DBT) fracture occurred as the test temperature declined, and the critical temperature decreased as the joint size decreased. All of the results suggest that the small-sized joints are more robust at low temperatures under shear loading.

Underfill material property dependence of lifetime and mechanical behavior of BGA package: EBSD and FEM investigations

This study experimentally and numerically investigated the endurance life and mechanical behavior of the ball grid array (BGA) packages according to the presence of underfill and the properties of underfill materials. Using non-underfill, medium Tg underfill (120 °C) and high Tg underfill (165 °C), we thoroughly investigated which underfill determines the reliability of BGA package structures. The presence or absence of the underfill fundamentally determines the reliability of the BGA package.

Optimization Method for Hot Air Reflow Soldering Process Based on Robust Design

The process design of hot air reflow soldering is one of the key factors affecting the quality of PCBA (Printed Circuit Board Assembly) component products. In order to improve the product quality during the design process, this paper proposes a robust optimization-based finite element simulation analysis method including significant influencing factor screening, robustness evaluation, robust optimization, and reliability verification for the reflow soldering process. The simulation model of the reflow soldering process temperature field based on experiments is constructed and validated. Sensitivity analysis is used to select important influencing factors, such as the last five set temperature zones (T5 to T9) in the reflow oven and the thermal properties of materials such as PCBs (printed circuit boards), BGAs (ball grid arrays), and solder paste, as well as noise factors like the heating environment during the soldering process. Several surrogate models are used to construct the response surface, and the optimal fitting scheme is selected to effectively avoid poor fitting caused by inappropriate surrogate models. The 6σ robust optimization approach is introduced to evaluate and optimize the robustness of the process design parameter where the heating factor is chosen as the optimization target. The reliability analysis method is employed to validate the product quality. This paper establishes a comprehensive robustness analysis method for hot air reflow soldering, effectively reducing design costs and addressing the lack of robustness analysis in the current hot air reflow soldering process design.