Baliga's Figure Of Merit Research Articles

Lateral variation doped wide bottom trench gate IGBT for reduced on-resistance with improved gate charge

In this paper, novel concept of lateral variation doping profile in the drift region for IGBT is presented. The variation profile divides the drift region in four sections in such a way that highly doped p+ and n+ pillars are present at the center, while pillars with lesser concentration are situated at the drift region boundary. Higher concentration below the channel region, enables the presence of more free charges in the conduction path thereby reducing the specific resistance (Ron.A) in the conduction path. The p- and n- section reduces the critical electric field at the corner and maintains the similar breakdown voltage in comparison with the conventional design despite of higher concentration doping profile at the middle. Proposed structure offers 19% improvement in current density and 16% reduction in Ron.A. Lateral variation doped structure also able to reduce on-state voltage drop (Von) by 15.38%. Along with the lateral doping concept, Proposed structure utilizes the broad oxide at the gate region in order to improve the switching performance. The increment in the oxide thickness reduces the gate to collector capacitance (CGC) and leads to reduces the gate to collector charge (QGC) by 30%. Reduction in gate charge also improve the switching performance of the devices and reduces the energy losses during the turn-off period. The 20% improvement in turn-off losses at same on-state voltage drop is observed. Additionally, 5% improvement in the on-state voltage drop is also achieved. Additionally, various figure of merit (FOM) is also evaluated. The Baliga's FOM and industrial FOM is improved by 19% and 55% respectively as compared to conventional design.

(Invited) A Path Toward Vertical GaN Superjunction Devices

GaN devices offer exciting competition to incumbent technologies to meet the growing demand for high power electronic devices. The wide bandgap of GaN makes it possible to achieve higher breakdown voltages and reduced on-resistances compared to traditional Si in unipolar devices, as predicted by the classical Baliga figure of merit (BFOM). However, unipolar performance limits can be circumvented using the superjunction (SJ), which has been demonstrated experimentally in both Si and SiC. Due to the current difficulties with selective area doping in GaN, experimental reports of vertical GaN SJs are lacking. In response, we propose the use of the lateral polar junction (LPJ), which is unique to III-Nitrides, to create next-generation vertical GaN SJ devices. We develop a model that provides first order design equations for such a device, and validate it using TCAD simulations of a 1.2 kV diode. A proposed manufacturing approach for LPJ-based GaN SJ is provided.

An insulated gate bipolar transistor with three-layer poly gate for improved figure of merit

In this study, an insulated gate bipolar transistor (IGBT) with three-layer poly gate is proposed and investigated by TCAD simulation. Here, gate is spilt in two different workfunction materials of N+ poly ( $$\phi _{g}$$ = 4.17 eV) and P+ poly ( $$\phi _{g}$$ = 5.25 eV). Lower workfunction poly layer is sandwiched between higher workfunction poly, connected via a single metal. The gate oxide thickness is varied in x-direction. This leads to improvement in transconductance and reduction in miller capacitance. Thin oxide near the emitter serves good control over the charge carriers in the channel. This deployment of dual material gate in proposed device results in 36% reduction in area-specific on-resistance without any degradation in breakdown voltage. In addition to this, proposed device exhibits improved transient characteristics with 18.5% and 60% reduction in turn-off time and delay, respectively, as compared to conventional device. Further, the turn-off energy loss is reduced by 23.5% and 29.09% reduction in on-state voltage drop is achieved. Furthermore, proposed device offers 23%, 58%, and 30% improvement in FOM1, Baliga figure of merit (BFOM), and FOM2, respectively.

Ultrawide-Bandgap Nanoscale p-n Junction Field Effect Transistors of GaN / β-Ga2O3 for High Power Operation

β-Ga2O3 is emerging as a next-generation ultrawide bandgap materials for high efficiency power devices, owing to its large direct band gap (4.85eV), high breakdown field (~ 8 MV / cm) and excellent thermal∙chemical stability. The Baliga’s figure-of-merit (BFOM) of β-Ga2O3 is 3214.1, which is superior to other materials such as GaN (846.0) or SiC (317.1). In addition to superior characteristics, the availability of large crystalline substrates with controllable carrier concentrations from semi-insulation to n-type is responsible for many of the recent improvements that will utilize β-Ga2O3 as near future power device material. However, potential of β-Ga2O3 has not yet been fully explored because of the low thermal conductivity of β-Ga2O3 and absence of p-type doped β-Ga2O3. To overcome this limitation, integration with p-type materials with excellent thermal conductivity is being studied.Although β-Ga2O3 is not a van der Waals material, β-Ga2O3 can be mechanically exfoliated into a thin layer due to the large anisotropy of the unit cell from the single crystal substrate. The mechanically exfoliated flakes with high crystallinity have no significant strains due to lattice mismatch with the underlying substrate, which has great advantages in integration with other substrates and miniaturization of devices. Based on these advantages, various studies have been conducted to fabricate nanoscale devices that utilize the excellent properties and overcome the disadvantages of β-Ga2O3, through integration of exfoliated flakes with p-type substrates such as diamond and SiC. In our work, nanoscale junction field effect transistors (JFETs) were fabricated by utilizing p-n junction between β-Ga2O3 flakes and p-type GaN substrate.β-Ga2O3 / GaN JFETs were fabricated by using the β-Ga2O3 flakes exfoliated from single-crystal bulk substrate. Dielectric layer between GaN substrate and β-Ga2O3 metal electrode were defined by hydrogen silsesquioxane (HSQ), followed by e-beam patterning. β-Ga2O3 flakes were precisely transferred on HSQ pattern by PDMS-assisted dry transfer method. Ohmic metal of GaN (Ni/Au) and β-Ga2O3 (Ti/Au) was deposited by e-beam evaporator, followed by rapid thermal annealing to confirm ohmic contact of GaN and β-Ga2O3, respectively. Fabricated β-Ga2O3 / GaN JFETs showed outstanding electric properties with high rectification ratio between p-n junction of GaN and β-Ga2O3. Fabricated devices showed excellent n-type DC output and transfer characteristics even after few weeks, which shows excellent long-term air-stability. Robustness and stability of fabricated devices under harsh conditions were confirmed by operating devices under various temperature. Thermal distribution and electric field simulation of fabricated JFETs were performed to confirm the effect of GaN substrate in thermal issues. In this study, we present the way to integrating β-Ga2O3 devices with p-GaN, resolving issues of thermal conductivity and p-type doping without lattice mismatch or defects. The details of our work will be discussed in the conference.

1.4kV Planar Gate Superjunction IGBT with Stepped Doping Profile in Drift and Collector Region

In this paper, stepped doping profile in alternate pillars and collector region of superjunction IGBT structure is presented. The proposed device structure consists of lightly and heavily doped region in upper and lower part of drift region. In addition to this, the collector layer doping concentration reduces along the x-direction. The initiation point of avalanche multiplication shifts from top and bottom corners to middle of the drift region. Due to this structural design, we have revealed that the area specific on resistance of proposed device is reduced by 16% at 300 K and 10% at 400 K without affecting breakdown voltage. Simulation results determine that 34.9% reduction in miller capacitance at room temperature in propose device. Additionally, 40% improvement in switching delay and 17% reduction in turn-off time is resulted. Baliga’s Figure of Merit (BFOM) and other technology Figure of Merit (FOM) are improved by 19% and 38% respectively. Furthermore, Eoff is reduced by 17.84% in proposed device.

Meandering Gate Edges for Breakdown Voltage Enhancement in AlGaN/GaN High Electron Mobility Transistors

Herein, a unique device‐design strategy is reported for increasing the breakdown voltage and hence Baliga figure of merit (BFOM) of III‐nitride high electron mobility transistors (HEMTs) by engineering the gate edge toward the drain. The breakdown of such devices with meandering gate‐drain access region (M‐HEMT) are found to be 62% more compared with that of conventional HEMT whereas the on‐resistance suffers by 76%, leading to an overall improvement in the BFOM for by 28%. The 3D technology computer‐aided design simulations show that the decrease in the peak electric field at the gate edge was responsible for increased breakdown voltage.

Trench IGBT with stepped doped collector for low energy loss

In this paper, a novel technique of variation doping profile in collector region for trench IGBT is proposed. The collector region is segregated in three sections such that the section with higher concentration lies towards emitter side while section with lower concentration lie towards gate side. The presence of lightly doped collector section increases the recombination rate by injecting lesser charge carrier leading to reduction in carrier lifetime. This effect further improves turn-off process for proposed device. However, due to increased recombination rate, collector current density reduces. But, this reduction is counter balanced by heavily doped collector section which injects higher charge carriers and maintains current flow through proposed device. The electrical characteristics of proposed and conventional device is simulated and analyzed. It is inferred that proposed device exhibits 48% reduction in turn-off time further minimizing energy loss by 53.3%. The lower doping profile of collector region also reduces corner electric field but due to p++-col section the net electric field increases hence, improving the breakdown voltage by 8.7%. Additionally, proposed structure exhibits 16.7% increment in Baliga figure of merit as compared to conventional design.

Experimental Study of High Performance 4H-SiC Floating Junction JBS Diodes

This paper reports the demonstration of a high performance 4H-SiC floating junction junction barrier Schottky (FJ_JBS) rectifier with a 30μm, 6×10 15 cm -3 -doped epitaxial layer. Extensive simulations have been performed to design, optimize and analyze the structure of the FJ_JBS rectifier. The fabricated FJ_JBS shows that breakdown voltage (BV) and differential R on,sp are 3.4 kV, yielding the highest BV value reported for 4H-SiC FJ diodes, and 5.67 mΩ·cm 2 , respectively. Compared with the conventional JBS, the BV value of FJ_JBS increases by 33.3% and the R on,sp only slightly rises by 6.2%. The corresponding Baliga figure-of-merit (BFOM) (4 BV 2 /R on_sp ) of this FJ_JBS diode is 8.16 GW/cm 2 .

Experimental study and characterization of an ultrahigh-voltage Ni/4H–SiC junction barrier Schottky rectifier with near ideal performances

Abstract An ultra-high voltage SiC JBS (silicon carbide junction barrier Schottky) rectifier utilizing a novel area-efficient multi-zone gradient modulated field limiting ring (MGM-FLR) technique have been fabricated, measured, and analysed in this paper. Ni-Schottky metal with a high barrier height is used to achieve a better trade-off between the on-resistance and the breakdown voltage. MGM-FLR, which is implanted simultaneously with the P+ grids within the active area of the device, forms a similar variation of lateral doping to mitigate the electric field crowding caused by junction curvature effect and obtains a maximum blocking voltage with minimally sized edge termination area. The fabricated device is tested to obtain a specific on-resistance is 140 mΩ cm2 and a reverse breakdown voltage of 14 kV with the leakage current of 10 μA, which is quite close to the theoretical value of parallel plane junction calculated using the device parameter of drift region 100 μm and the concentration 5 × 1014 cm−3. The highest Baliga's figure-of-merit (BFOM) 5.6 GW/cm2 was obtained for the proposed devices. Furthermore, the distribution of the extracted barrier height versus ideality factor on the wafer are demonstrated using I–V method. Impacts of ring spacing and zone of MGM-FLR termination on SiC device reverse blocking performance are also investigated in detail.

Theoretical and Experimental Study of 13.4 kV/55 A SiC PiN Diodes with an Improved Trade-Off between Blocking Voltage and Differential On-Resistance.

In this paper, a 13.4 kV/55 A 4H-silicon carbide (SiC) PiN diode with a better trade-off between blocking voltage, differential on-resistance, and technological process complexity has been successfully developed. A multiple zone gradient modulation field limiting ring (MGM-FLR) for extremely high-power handling applications was applied and investigated. The reverse blocking voltage of 13.4 kV, close to 95% of the theoretical value of parallel plane breakdown voltage, was obtained at a leakage current of 10 μA for a 100 μm thick, lightly doped, 5 × 1014 cm−3 n-type SiC epitaxial layer. Meanwhile, a fairly low differential on-resistance of 2.5 mΩ·cm2 at 55 A forward current (4.1 mΩ·cm2 at a current density of 100 A/cm2) was calculated for the fabricated SiC PiN with 0.1 cm2 active area. The highest Baliga’s figure-of-merit (BFOM) of 72 GW/cm2 was obtained for the fabricated SiC PiN diode. Additionally, the dependence of the breakdown voltage on transition region width, number of rings in each zone, as well as the junction-to-ring spacing of SiC PiN diodes is also discussed. Our findings indicate that this proposed device structure is one potential candidate for an ultra-high voltage power system, and it represents an option to maximize power density and reduce system complexity.

(Invited) Performance Evaluation of III-N Bipolar Switches Grown on GaN Substrates

The successful development of III-V nitride materials systems has led to active research of advanced electronic devices in the recent decades. III-nitride (III-N)-based devices have a bandgap engineering flexibility, large energy gap, direct band structure, and high carrier mobility when compared to Si- and SiC -based devices, providing new performance improvement opportunities for high-speed and energy-efficient electronics. Today, commercial GaN HFETs are available for microwave power amplifiers and power electronic circuits. On the other hand, the development of bipolar transistors and the related switch technologies are essential to fully exploit the potential of III-N materials systems. For instance, insulated-gate-bipolar transistors would require integrated bipolar transistor and unipolar transistor structures. The development of III-N bipolar switches in either two-terminal or three-terminal forms have therefore been actively sought. To this end, power switches that conduct the electric current in the vertical form are beneficial to achieve the ultimate Baliga’s Figure of Merit (BFOM) for switching. For GaN bipolar power switches development, low-defect-density native substrates, high-quality epitaxial growth technology, and proper device design and fabrication have become major focus areas of research. Early development of heterojunction bipolar transistors (HBTs) using GaN/InGaN heterojunctions at Georgia Tech showed promising device performance. These devices exhibited high-current gain of >100, high current drive density of >100 kA/cm2, and high d.c. power handling capability of > 3 MW/cm2. Small-signal microwave amplification with a cut-off frequency (f T) of 8GHz was reported. In this presentation, we will review the development status of III-N bipolar switches and use GaN rectifiers as a case study to discuss the device performance pertinent to the choices of GaN substrates prepared by different methods. The device structures were grown and fabricated at Georgia Tech and the device performance correlation with respect to the substrates were evaluated. High-power operation was demonstrated for homojunction GaN PIN rectifiers grown on a 2-inch bulk GaN substrate using a metalorganic chemical vapor deposition (MOCVD) reactor. The GaN substrate was prepared using a near-equilibrium ammonothermal (NEAT) method. The device fabrication employed an ion-implantation isolation, field plate, and electroplated copper electrodes. The fabricated devices have dimensions up to 1.1 mm in diameter and showed uniform V on of 3.6±0.1 V and an ideality factor of 2.08. A blocking voltage (BV) of >1.2 kV and the on-state resistance (R ON A) of 0.4 mΩ·cm2 were measured. For PIN rectifiers with a dimension of 1.1 mm in diameter, we reported a BV of 1,200 V and an on-state current drive of greater than 11 A (1 kA/cm2). These results demonstrated the feasibility of using bipolar carrier transport mechanisms and PN junctions in III-N devices for power amplifications and switching circuits.

A Novel Kilovolts GaN Vertical Superjunction MOSFET With Trench Gate: Approach for Device Design and Optimization

In this paper, a gallium nitride (GaN) vertical superjunction (SJ) MOSFET with trench gate is proposed and studied by the TCAD simulation. In order to achieve the typical electric field ( $E$ -field) modulation effect by the P+/N/N+ structure in the conventional Si SJ-MOS, the P-GaN/unintentional doped (UID)-GaN/N+-GaN stack is alternatively used by taking into account the unavailability of P+-GaN. In this manner, the P-GaN and N+-substrate serve as the field-stop (FS) layers in the proposed GaN SJ-MOS. In the forward bias, the enhancement-mode function of the device is enabled by the gated side-wall and aperture composite channel that leads to a 1.47-V threshold voltage of the device. In the reverse bias, the breakdown of the device is governed by two mechanisms: 1) the punchthrough (PT) in the top P-GaN/N-drift junction due to the possible under design of the P-GaN thickness; 2) the avalanche breakdown triggered by high $E$ -field due to the possible under design of the bottom UID-GaN thickness. Hence, from the uniform $E$ -field distribution point of view, a device optimization approach for GaN vertical SJ-MOS is proposed. The hole and electron densities of P-GaN and N-drift are optimized to achieve a uniform $E$ -field distribution in the device both in the lateral and vertical directions, which is found to be $6 \times 10^{16}$ cm $^{-3}$ . Moreover, the thickness ratio of P-GaN/UID-GaN is designed to obtain an identical intrinsic breakdown for the top P-GaN/N-drift junction and bottom UID/N-drift region, which enables the maximum Baliga’s figure-of-merit (BFOM) of the device. The concept of device design and optimization is of great interests for GaN vertical device for over kilovolts applications.

Workfunction engineered stepped gate SJ UMOS with reduced specific resistance for high speed applications

In this paper, trench superjunction MOS (SJ UMOS) utilizing workfunction engineered stepped gate for performance enhancement is proposed. N+ polysilicon (Φm = 4.17 eV) layer in between two P+ polysilicon (Φm = 5.25 eV) layer connected by a metal gate is incorporated in the proposed device. Additionally, gate oxide thickness is increased in steps from source to drain resulting in enhanced gate-source capacitance and reduced gate-drain capacitance. The electrical behavior of conventional and proposed device is investigated using 2D numerical simulations. The results indicate 19.5% reduction in specific resistance without degrading the breakdown voltage. Further, the proposed structure also exhibits 28.9% reduction in specific gate to drain charge, 30.5% increment in gate to source charge and 54% reduction in switching delay. In addition to this, Baliga’s figure of merit (BFOM) along with other technology figure of merit (FOM) has also been evaluated, demonstrating a 26% increment in BFOM. The significant improvement in FOM is attributed to reduced specific resistance and gate to drain charge of the proposed structure. Additionally, the impact of temperature on device performance is also evaluated and no degradation in the device parameters is observed.

Design and Optimization of SiC Super-Junction MOSFET Using Vertical Variation Doping Profile

In this paper, uniformly doped drift region of silicon carbide (SiC) super-junction (SJ) MOSFET is replaced with vertical variable doping profile (VVD) to achieve a better tradeoff between breakdown voltage (BV) and specific ON-resistance ( ${R}_{\text {sp,on}}$ ). While it is known that the SJ device consists of two vertical columns of n- and p-type, SJ VVD feature lies in increasing the doping concentration from top to bottom in the N-column and vice-versa in the P-column within the drift region. The proposed SJ VVD allows $\text {R}_{{\text {sp, on}}}$ to reduce further due to increased average doping concentration in conducting N-column and BV to increase further due to shifting of an electric field from corners to the center of the drift region. BV and ${R}_{\text {sp,on}}$ improved by 10% in an SJ VVD MOSFET and these parameters follow linear relationship similar to SJ MOSFET. The 2-D numerical simulations from Synopsys TCAD are used for investigating the static and dynamic characteristics of the device. In addition to 30% improvement in Baliga figure of merit, 35% improvement is obtained over SJ MOSFET in turn on and turn off switching energies for a clamped inductive circuit at 1200 V–20 A. Improved dynamic characteristics of SJ VVD can be attributed to reduction in gate charge ( ${Q}_{g}$ ) and miller capacitance ( ${c}_{\text {rss}}$ ) compared to SJ MOSFET.

Simulation design of high Baliga's figure of merit normally-off P[sbnd]GaN gate AlGaN/GaN heterostructure field effect transistors with junction field plates

In this paper, we conducted a numerical analysis on novel Normally-off PGaN gate AlGaN/GaN heterostructure field effect transistors with junction field plates (JFP-HFET). The breakdown voltage (BV) was significantly improved with the introduction of the junction field plate (JFP), which can make a rectangular distribution of the electric field in the GaN channel between the gate and the drain. The highest BV of 1340 V of JFP-HFET could be achieved with the gate to the drain distance Lgd = 6 μm, the length of the P-type region of the JFP Lp = 5.8 μm, the thickness of the JFP Tj = 500 nm, the doping concentration of P-type region of the JFP Np = 1 × 1017 cm−3, and the Al fraction of the AlGaN JFP xAl = 0.25. The optimum parameters of the JFP-HFET were achieved by considering both the principle of charge balance and the practical fabrication of the III-V devices. The highest Baliga's figure of merit (BFOM) 1.2 GW/cm2 was obtained under the conditions of Lgd = 6 μm, Lp = 5.8 μm, Tj = 100 nm, Np = 6 × 1017 cm−3, and xAl = 0.3. CV, turn-on and turn-off processes revealed that the JFP-HFET showed better switching characteristics than that of the HFET with metal field plate.

A 4H-SiC junction barrier Schottky diode with segregated floating trench and super junction

A 4H-SiC Junction Barrier Schottky Diode with Segregated Floating Trench and Super Junction (S-FT SJ JBS) is presented in this paper. By adopting segregated integrated trench and super junction, the high electric field not only focus on the bottom of trench but also gathers in the top of trench and the edge of super junction, therefore the distributions of the high electric field is more uniform, and thus to substantially improve the breakdown voltage (BV). By using the floating trench, the area of schottky contact is enlarged, thus the density of current is increased in the on state, and the specific on-resistance (Ron,sp) of the device is ultimately decreased. The results of simulation show that the BV and Ron,sp of S-FT SJ JBS diode are 1891V and 0.16 mΩ cm2, and the BV is improved by 29.5% and the Ron,sp is decreased by 50% compared with I-FT SJ JBS diode. The Baliga figure-of-merit (BFOM) of S-FT SJ JBS diode is 894 W·cm−2 which is increased by 236.1% compared with I-FT SJ JBS diode.

820-V GaN-on-Si Quasi-Vertical p-i-n Diodes With BFOM of 2.0 GW/cm2

In this letter, we demonstrate GaN-on-Si p-i-n diodes with high breakdown voltage and state-of-the-art Baliga’s figure of merit (BFOM) among GaN-on-Si vertical devices. The growth and doping of the GaN drift layer were optimized, leading to a remarkable electron mobility of 720 cm2/Vs for a Si doping level of $\text {2} \times \text {10}^{\text {16}}$ cm−3. With a 4 $\mu \text{m}$ -thick drift layer, we achieved an excellent breakdown voltage of 820 V and ultra-low specific on resistance ( ${R}_{\text {on,sp}}$ ) of 0.33 $\text{m}\Omega $ cm2. This results in a BFOM of 2.0 GW/cm2, the highest value reported for GaN-on-Si vertical diodes. These results reveal the excellent prospect of GaN-on-Si for cost-effective vertical power devices.

The GaN trench gate MOSFET with floating islands: High breakdown voltage and improved BFOM

A novel GaN trench gate (TG) MOSFET with P-type floating islands (FLI) in drift region, which can suppress the electric field peak at bottom of gate trench during the blocking state and prevent premature breakdown in gate oxide, is proposed and investigated by TCAD simulations. The influence of thickness, position, doping concentration and length of the FLI on breakdown voltage (BV) and specific on-resistance (Ron_sp) is studied, providing useful guidelines for design of this new type of device. Using optimized parameters for the FLI, GaN FLI TG-MOSFET obtains a BV as high as 2464 V with a Ron_sp of 3.0 mΩ cm2. Compared to the conventional GaN TG-MOSFET with the same structure parameters, the Baliga figure of merit (BFOM) is enhanced by 150%, getting closer to theoretical limit for GaN devices.

Simulation of 4H-SiC Trench Junction Barrier Schottky Diodes with High-k Dielectrics

In this paper, a novel 4H-SiC trench JBS (TkJBS) with high-k semi-insulating polycrystalline silicon (SIPOS) is proposed. By adopting a new high-k dielectrics-trench structure, the peak electric field at the corner of P+ region (COP) in Silicon Carbide (SiC) can be weakened significantly, and the device breakdown voltage can be enhanced significantly. SiC TkJBS has a 60.7% higher breakdown voltage (BV) and a 110.6% higher Baliga’s figure of merit (BFOM) than the conventional SiC JBSs, and the surface electric field (Esf) of the SiC TkJBS is 0.73 MV/cm lower than it at breakdown voltages, resulting in a much lower tunneling current (Ir). The reverse recovery characteristics of SiC TkJBS are also slightly better than those of the SiC JBS. It is indicated that SiC TkJBS is a promising candidate for next-generation high power diodes.

Investigation of SiC trench MOSFET with floating islands

The silicon carbide trench metal-oxide-semiconductor field-effect transistors (SiC UMOSFET) with P + floating island (FLI) which shields the gate oxide at the bottom of the gate trench from the high electric field during the blocking state and enhances the breakdown voltage (BV), is presented in this study using two-dimensional simulations. The effects of doping concentration, length and position of FLI on BV, electric field distribution and specific on-resistance ( R on,sp ) are studied, thereby providing particularly useful guidelines for the design of this new type of device when considering the breakdown of the gate oxide layer. For the suitable device design, the results indicate that BV and Baliga figure of merit are, respectively, increased by 150 and 439% compared with a conventional SiC UMOSFET. At the same time, the SiC FLI UMOSFET has smaller gate-drain capacitance and better switching performance compared with the conventional UMOSFET on the condition of the same drift layer parameters. FLI introduced have almost no influence on the recovery characteristics of body diode.