Backside Processing Research Articles

Cleaning and Particle Challenges in the Temporary Bonding and Debonding Process

The demands of 5G, Internet of Things and other global technology trends, combined with the increasing cost of scaling down process nodes, have created a shift towards more integrated packaging requirements. The emergence of advanced packaging technologies, such as Fan-Out Wafer Level Packaging (FOWLP), 2.5D/3D IC packaging, and heterogenous integration, brings potential for smaller form factors with increased functionality and bandwidth [1]. Backside processing or thinning of the device wafer is often needed for enabling these technologies. This requires the device wafer be adhered to a rigid carrier wafer using a temporary bonding material (TBM) for mechanical support during handling and processing. Following carrier release, the TBM must be thoroughly removed and cleaned from the device wafer. Many of these adhesives are exposed to high-power lasers or elevated temperatures, making removal more challenging. Sub-micron particle level clean demands for temporary bonding material (TBM) removal are also reaching standards typically reserved for front-end-of-line (FEOL) processing. This is especially crucial in 3D processes such as hybrid bonding where feature and pitch sizes are nearing <1 µm and insufficient cleaning can lead to failures in subsequent bonding processes [2]. Thus, careful consideration of all processing steps is necessary to meet stringent particle demands. This work investigates the removal of coated and baked TBM on silicon wafers, with an emphasis on processing conditions that obtain best particle results. Several chemistries were assessed at the beaker level by performing coupon-level studies and measuring surface properties. Based on these findings, studies with 300-mm wafers were performed using a customizable single-wafer processing tool.

Systematic Study and Review of InP‐based Tera‐Hertz‐ICs Fabrication Process Technology for Beyond 5G/6G Wireless Communication Networks

Next‐generation “Beyond 5G (B5G)/6G” wireless network systems have been researched and developed for meeting the rapid growth of mobile traffic. A high‐yield fabrication process of InP‐based transistors and tera‐hertz monolithic integrated circuits with 300 GHz operation is reported, which is a candidate frequency for “Beyond 5G/6G” network systems. The main focus is on a high‐yield and reproductive fabrication process of InP‐based high electron mobility transistors (HEMTs) while revisiting previous studies. The DC and radio frequency characteristics of fabricated InP‐HEMTs from the viewpoint of integrating circuits are described. Then, high‐frequency performances of ft = 280 GHz and fmax = 860 GHz in the bias conditions of Vgs/Vds = 0.2/1.1 V with good uniformity are obtained. Finally, InP‐based 300 GHz‐band mixer and power amplifiers are introduced, to which a backside process is also applied for ensuring their stability and enhancing output power.

3D backside integration of FinFETs: Is there an impact on LF noise?

This paper compares the low-frequency noise performance of backside integrated pFinFETs versus their regular frontside-only processed counterparts. We report that no degradation of the dominant flicker noise is observed, comparing front- versus backside processed transistors. At the same time, application of a post backside processing annealing step(s) is shown to enable an improvement of the DC input characteristics and the low-frequency noise power spectral density of the devices.

Advancements, Versatility, and Flexibility of Dual-Layer Material System for Advanced Packaging Applications

Integrated circuits (IC) have seen a major shift in development within the past 10-20 years with traditional lithography methods showing a drastic increase in development time for more advanced nodes, as well as an exponential increase in cost to achieve the same performance gains as before. The increase in cost and the decline in development in lithography have resulted in looking at advanced packaging technologies to achieve the same performance gains by changing the way IC design is approached. The look towards advanced packaging technologies for the future in terms of increasing performance for a substantially lower cost has resulted in considering the IC as a system of components working intertwined with each other rather than as individual components. This shift in mindset has resulted in technologies such as system in package (SiP), package on package (PoP), and fan-out wafer-level packaging (FOWLP). One advanced packaging technology that plays a critical role enabling these aforementioned technologies is temporary bond and debond (TB/DB). TB/DB’s crucial role in advanced packaging is due to the enablement of backside processing such as wafer thinning, bumping of the wafer, die stacking, and chemical vapor deposition/physical vapor deposition (CVD/PVD)–type processes by the use of a support carrier wafer. The support carrier wafer also allows for the use of highly warp-prone materials such as epoxy mold compound (EMC), which are critical in FOWLP applications, by reducing the overall warpage of the entire wafer stack. To utilize the support carrier wafer, a robust material solution is required to allow for the wafers to be bonded together and subsequently released after backside processing by one of the primary separation methods of thermal slide, mechanical, or laser debond. Brewer Science has designed and developed a dual-layer temporary bonding system. This system consists of two materials, a thermoplastic layer that is typically coated on the device, and a thermoset layer which is typically coated on the carrier. The materials developed for the dual-layer system demonstrate very good performance in very high temperature applications, EMC wafer handling, and device thinning to sub-20 µm. In this paper, we will summarize their capabilities and introduce how adhesion between the two temporary layers can be adjusted by material design. We will also cover a new feature of the thermoset layer that can be patterned to allow for the use of a patterned bonding material for TB/DB-type applications.

Two-sided manual machining method for three-axis CNC milling machine for small and medium-sized enterprises

Small and medium-sized enterprises (SMEs) have a big role in Indonesian economic development. The government has set four strategies in an effort to boost Indonesian economic development. One of the four strategies mentions the SMEs, and the other mentions the use of 4.0 technology. Working capital has been the main issue need to be considered in the SMEs. Thus, the affordability must be considered in the use of 4.0 technology in SMEs. One of the 4.0 technologies that are possible to be used in the SMEs is a three-axis milling machine. One of the limitations of the machine is that it cannot do the back-side machining process. The paper examines the possibility of manual back-side machining on the three-axis milling machine without adding a rotary axis. Four methods were conducted by adding two-point markings on the x-axis, two-point markings on the y-axis, four-point markings on the x- and y-axis, and four-point markings on the x- and y-axis plus a series of offsetting processes. After conducting several qualitative observations and measurements on the mismatched position of the front and the back machining, and also analyzing the problems that emerged during the processes of the four different methods, it is concluded that adding four points markings on the x- and y-axis plus doing a series of offsetting processes is the best method to have two-sided manual machining with three-axis computer numerical control (CNC) milling machine.

3D TSV hybrid pixel detector modules with ATLAS FE-I4 readout electronic chip

The through silicon via (TSV) technology has been introduced in a wide range of electronic packaging applications. Hybrid pixel detectors for X-ray imaging and for high-energy physics (HEP) can benefit from this technology as well. A 3D TSV prototype using the ATLAS FE-I4 readout electronic chip is described in this paper. This type of readout chip is already prepared for the TSV backside process providing a TSV landing pad in the first metal layer of the backend-of-line (BEOL) layer stack. Based on this precondition a TSV backside via-last process is developed on ATLAS FE-I4 readout chip wafer. The readout chip wafers were thinned to 100 µm and 80 µm final thickness and straight sidewall vias with 60 µm in diameter has been etched into the silicon from wafer backside using deep reactive ion etching (DRIE). The filling of the TSVs and the formation of the wafer backside interconnection were provided by a copper electroplating process. ATLAS FE-I4 readout chips with through silicon vias has been successfully tested, tuned and operated. In addition, hybrid pixel detector modules have been flip chip bonded using ATLAS FE-I4 TSV readout chips and planar sensor chips. After mounting the bare modules onto a support PCB, its full functionality has been verified with a source scan.

Substrate Effects on the Electrical Properties in GaN-Based High Electron Mobility Transistors

We report the electrical characteristics of GaN-based high electron mobility transistors (HEMTs) operated on various substrates/films. For the detailed investigation and comparison of the electrical properties of GaN-based HEMTs according to the substrates/films, GaN-based HEMTs were processed using 4-inch sapphire substrates and separated from their original substrates through the laser lift-off technique. The separated AlGaN/GaN films including processed GaN-based HEMTs were bonded to AlN substrate or plated with a 100 µm-thick Cu at the back-side of the devices since AlN substrate and Cu film exhibit higher thermal conductivity than the sapphire substrate. Compared to the sapphire substrate, DC and RF properties such as drain current, transconductance, cut-off frequency and maximum oscillation frequency were improved, when GaN-based HEMTs were operated on AlN substrate or Cu film. Our systematic study has revealed that the device property improvement results from the diminishment of the self-heating effect, increase in carrier mobility under the gated region, and amelioration of sheet resistance at the access region. C(V) and pulse-mode stress measurements have confirmed that the back-side processing for the device transfer from sapphire substrate onto AlN substrate or Cu film did not induce the critical defects close to the AlGaN/GaN hetero-interface.

Photonic Debonding for Wafer-Level Packaging

Abstract Temporary bonding and debonding (TB/DB) processes have emerged as promising solutions in wafer-level packaging technology. These processes offer a pathway to wafer thinning and subsequent backside processing, which are crucial in enabling heterogenous integration using technologies such as 3D through-silicon-vias (TSVs) and fan-out wafer-level packaging. These are critical for overall device miniaturization and increased performance. In this work, a novel photonic debonding (PDB) method and the corresponding bonding material are presented. PDB enhances the TB/DB process by overcoming many of the disadvantages associated with traditional debonding methods. PDB uses pulsed broadband light (200 nm – 1100 nm) from flashlamps to debond temporarily bonded wafer pairs with glass as the carrier wafer. These flashlamps generate high-intensity pulses of light (up to 45 kW/cm2) over short time intervals (~100 μs) to facilitate the debonding. Feasibility of the PDB in the TB/DB process is demonstrated by successfully debonding thinned (<70 μm) silicon wafers from glass carriers. Post-debond cleaning of the thinned wafers and carriers is evaluated. With uniform, large-area illumination (75 mm x 150 mm) per flashlamp and with the ability to concatenate lamps to increase the illumination area of the PDB tool, the PDB method offers a high-throughput and low-cost debonding solution for both wafer-level and panel-level packaging technologies.

The silicon sensors for the High Granularity Calorimeter of CMS

The installation of the High-Luminosity Large Hadron Collider (HL-LHC) presents unprecedented challenges to experiments like the Compact Muon Solenoid (CMS) in terms of event rate, integrated luminosity and therefore radiation exposures. To cope with this new environment, new detectors will be installed during the CMS Phase 2 Upgrade, including the replacement of the calorimeter endcaps with the “High Granularity Calorimeter” (HGCAL), which contains silicon sensors and scintillators as active elements. The silicon sensors will be produced in an 8” wafer process, which is new for high-energy physics, so it demands extensive quality verification. A first batch of prototype sensors underwent electrical tests at the institutes of the CMS Collaboration. Testing revealed major problems with the mechanical stability of the thin backside protective layer, that were not seen in earlier 6” prototypes produced by a different backside processing method. Following these results, the HGCAL group introduced the concept of ”frontside biasing”, allowing testing of the sensors without exposing its backside, verified the applicability, and adapted the prototype design to apply this method in series production.

Research on a Ka‐Band MEMS Power Sensor Investigated with an MEMS Cantilever Beam

In this work, a novel high overload Ka-band power sensor with a Micro-electro-mechanical system (MEMS) cantilever beam is investigated in order to improve the measurement dynamic range and the bandwidth. The fabrication of the Ka-band power sensor is divided into front side and back side processing with a combination of surface and bulk micromachining of GaAs. The low-power measurement reveals that the terminating-type sensitivity is close to 0.081, 0.076 and 0.072mV/mW at 34, 35 and 36GHz, respectively. The high-power measurement indicates that the capacitivetype sensitivity is around 4.9fF/W at Ka-band. The overload power measurements show that the MEMS cantilever beam can improve the dynamic range by increasing the top end of the range into no less than 200mW, and enhance the bandwidth by increasing the top end of the range into no less than 36GHz. There is an important reference value to achieve the high overload and wide frequency band for the thermoelectric microwave power sensors.

A 4-tap global shutter pixel with enhanced IR sensitivity for VGA time-of-flight CMOS image sensors

An indirect time-of-flight (ToF) CMOS image sensor has been designed with 4-tap 7 μm global shutter pixel in back-side illumination process. 15000 e- of high full-well capacity (FWC) per a tap of 3.5 μm pitch and 3.6 e- of read-noise has been realized by employing true correlated double sampling (CDS) structure with storage gates (SGs). Noble characteristics such as 86 % of demodulation contrast (DC) at 100MHz operation, 37 % of higher quantum efficiency (QE) and lower parasitic light sensitivity (PLS) at 940 nm have been achieved. As a result, the proposed ToF sensor shows depth noise less than 0.3 % with 940 nm illuminator in even long distance.

Surface Stress Evolution in Through Silicon Via Wafer During a Backside Thinning Process

During Through Silicon Via (TSV) wafer backside thinning process, excessive surface stress will cause undue warpage or fracture of wafer in subsequent de-bonding step, and further impair the precision of following wafer stacking and packaging. Therefore, it is considerable to investigate the evolution mechanism of wafer stress and how to control it in backside thinning process. Aiming at the above problem, a calculation method is proposed in this paper to characterize surface stress of TSV wafer in a bonding structure, and the method has been confirmed by micro-Raman spectroscopy; Then, based on the method, the change of stress in TSV wafer during a whole backside thinning process is described, and the formation and evolution mechanism of surface stress is analyzed; At last, the stress control performance and corresponding mechanism explanation under different process parameters are demonstrated, and the optimal process condition is selected, which can release more than 80 percent of generated stress. In summary, this work can be regarded as a reference in three-dimension integrated circuit (3D IC) industry to select proper thinning conditions in order to obtain an optimized stress relief performance.

Feasibility Study of Wafer-Level Backside Process for InP-Based ICs

This paper reports wafer-level backside process technology, established with the intent to ensure stable operation of InP ICs in the submillimeter wavelength band, which generally suffer from ground bounce and substrate resonance. Our process consists of thinning a 3-in InP wafer, forming dense vias with interval cooling steps, backside metallization with single-level wiring and crack-free dicing. We investigate the effects of the backside process on InP-based heterojunction bipolar transistors and high electron mobility transistors. The results show that the backside process contributes to stable operation up to the 300-GHz range without any degradation of transistor characteristics.

The Monopix chips: depleted monolithic active pixel sensors with a column-drain read-out architecture for the ATLAS Inner Tracker upgrade

Two different depleted monolithic CMOS active pixel sensor (DMAPS) prototypes with a fully synchronous column-drain read-out architecture were designed and tested: LF-Monopix and TJ-Monopix. These chips are part of a R&D effort towards a suitable implementation of a CMOS DMAPS for the HL-LHC ATLAS Inner Tracker. LF-Monopix was developed using a 150nm CMOS process on a highly resistive substrate (>2 kΩ cm), while TJ-Monopix was fabricated using a modified 180 nm CMOS process with a 1 kΩ cm epi-layer for depletion. The chips differ in their front-end design, biasing scheme, pixel pitch, dimensions of the collecting electrode relative to the pixel size (large and small electrode design, respectively) and the placement of read-out electronics within such electrode. Both chips were operational after thinning down to 100 μm and additional back-side processing in LF-Monopix for total bulk depletion. The results in this work include measurements of their leakage current, noise, threshold dispersion, response to minimum ionizing particles and efficiency in test beam campaigns. In addition, the outcome from measurements after irradiation with neutrons up to a dose of 1×1015 neq / cm2 and its implications for future designs are discussed.

Influence of Glass Phase in Silver Paste on Metallized Contact Resistance between Rear Silver and Aluminum Electrodes of Crystalline Silicon PERC Cells

In the back-side metallization process of the passivated emitter and rear cell (PERC), the contact between the Ag rear electrode and Al rear electrode is an important factor for cell efficiency. In this paper, we report on the effect of Ag paste containing two types of oxide glass frit, V-B-Te and Pb-B-Si, on the Ag/Al contact, owing to their remarkable contrast with regard to the Ag/Al contact resistance. By combining the observation of the Ag/Al interface structure with the investigation on the interaction between glass and Al, glass transition temperature, and the distribution of glass phase in the Ag electrode, the influence of the glass phase on the contact resistance between rear Ag and Al electrodes was clearly elucidated.

Temporary and permanent bonding enables 3D integration of ultrathin wafers

Rising demand in memory is just one example how 3D integration is still gaining momentum. Not only the form factor but also performance is improved for several 3D integration applications by reducing the wafer thickness. Two competing process flows using thin wafers are to carry out for 3D integration today. Firstly, two wafers can be bonded face-to-face with subsequent thinning without the need to handle a thin wafer. However, some chip designs require a face-to-back stacking of thin wafers, where temporary bonding becomes an inevitable process step. In this case, the challenge of the temporary bonding process is different to traditional stacking on chip level, where usually the wafers are diced after debonding and then stacked on chip level, which means die thicknesses are typically in the range of 50 μm. The goal of wafer level transfer is a massive reduction of the wafer thickness. Therefore temporary and permanent bonding has to be combined to enable stacking on wafer level with very thin wafers. The first step is temporary bonding of the device wafer with the temporary carrier through an adhesive interlayer, followed by thinning and other backside processes. Afterwards the thinned wafer is permanently bonded to the target wafer before debonding from the carrier wafer. This can be repeated several times to be suitable for example a high bandwidth memory, where several layers of DRAM are stacked on top of each other. Another application is the memory integration on processors, or die segmentation processes. The temporary bonding process flow has to be very well controlled in terms of total thickness variations (TTV) of the intermediate adhesive between device and carrier wafer. The requirements for the temporary bonding adhesive include offering sufficient adhesion between device and carrier wafer for the subsequent processes. The choice of the material class for this study is the Brewer Science dual layer material comprising of a curable layer which offers high mechanical stability to enable low TTV during the thinning process and a release layer for mechanical debond process. The release layer must lead to a successful debond but prevent spontaneous debonding during grinding and other processes. Total thickness variation values of the adhesive will be analyzed in dependence of the adhesive layer thickness as this is a key criterion for a successful implementation at the manufactures. Besides the TTV the mechanical stability during grinding will be evaluated by CSAM to make sure no delamination has happened. For feasibility of the total process flow it is important that the mechanical debonding requires less force compared to the separation of the permanent bonded wafers. Other process parameters such as edge trimming of the device wafer as well as edge removal of the mechanical debond release layer are investigated.

Depleted fully monolithic active CMOS pixel sensors (DMAPS) in high resistivity 150 nm technology for LHC

Depleted monolithic CMOS11Complementary metal-oxide-semiconductor. active pixel sensors (DMAPS) have been developed to demonstrate their suitability as pixel detectors in the outer layers of the ATLAS Inner Tracker (ITk) pixel detector in the High-Luminosity Large Hadron Collider (HL-LHC). Two prototypes have been fabricated using a 150 nm CMOS technology on high resistivity (≥ 2 kΩcm) wafers. The chip size of 10 mm × 10 mm is similar to that of the current FE-I3 ATLAS pixel detector readout chip. One of the prototypes is used for detailed characterization of the sensor and analog front end circuitry of the DMAPS. The other one is a fully monolithic DMAPS, including fast readout digital logics that handle the required hit rate. To yield a strong homogeneous electric field within the sensor volume, back-side process of the wafer was tested. The prototypes were irradiated with X-rays up to a total ionization dose (TID) of 50 Mrad(SiO2) and with neutrons up to a 1 MeV neutron equivalent fluence of 1015 neq/cm2 to test non-ionizing energy loss (NIEL) effects. The analog front end circuitry maintained its performance after TID irradiation, and the hit efficiency at <10−7 noise occupancy was as high as 98.9% after NIEL irradiation.

Precision Au Electrocoating of Double Sided Aligned Si Gratings for High Energy X-Ray Phase Contrast Imaging

State of the art grating fabrication currently limits the maximum source energy that can be used in lab based x-ray phase contrast imaging (XPCI) systems. In order to move to higher source energies, and image thicker and more dense materials, new grating fabrication methods are needed. In previous work we developed a differentiating mold construction technique that replaces photodefinable organic templates1 with high aspect ratio silicon (Si) deep reactive ion etching (DRIE) followed by precision electrodeposition of gold (Au)2. Combining DRIE with precision electro-coating enabled the fabrication of un-supported Au absorption gratings with aspect ratios as high as 50:1 and grating areas as large as 100 cm2. Further pushing this grating fabrication to enable the use of higher energy x-ray sources, we developed a new modality for grating fabrication that involves precision alignment of etched features on both sides of a substrate, effectively doubling the thickness of the. This double sided grating fabrication approach was applied to make a phase grating out of DRIE Si. In this work, we couple double sided Si DRIE with precision gold (Au) electrodeposition to fabricate absorption gratings for high energy lab based XPCI. A 250 µm deep, 2 µm wide, and 4 µm pitch absorption grating was fabricated by aligning and etching 125 µm deep grating features on both sides of a Si wafer. The Si grating features are patterned and etched on an 8 µm pitch with the width of the Si features patterned at 2 µm. Fabricating uniform, high aspect ratio features across large areas on both sides of a substrate is difficult due to the need to temporarily protect one side of the grating while processing on the opposite side of the substrate. After both sides are processed, this temporary support material must be removed without damaging the gratings on either side of the substrate. At these feature sizes, surface tension forces after wet processing are strong enough to collapse the grating features and must be carefully avoided. Our integration approach for accommodating these challenges is illustrated in Figure 1. Alignment features are first patterned and etched into both sides of the substrate. The front side gratings are then patterned with reference to the front side field image alignment marks and etched into the Si. Plasma enhanced tetraethylorthosilicate (PETEOS) SiO2 is then deposited to protect the front side gratings during backside processing. The backside gratings are similarly aligned using the alignment marks on the backside of the substrate. After the gratings on both sides of the substrate are etched, a selective wet etch is used to remove the supportive oxide and a critical point dryer is used to prevent surface tension forces from damaging the Si bars. A conformal platinum (Pt) plating seed metal is deposited by atomic layer deposition (ALD) and Au is precisely electroplated at a uniform thickness of 2 μm throughout the depth of the Si grating. The Au serves as a high x-ray absorbing material finalizing the fabrication process. In this work, we provide details on our fabrication approach and measurements of our final grating geometries. Supported by the Laboratory Directed Research and Development program at Sandia National Laboratories, a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525. [1] - High Aspect Ratio Gratings for X-Ray Phase Contrast Imaging: J. Mohr, T. Grund, D. Kunka, J. Kenntner, J. Leuthold, J. Meiser, J. Schulz and M. Walter, International Workshop on X-Ray and Neutron Phase Imaging with Gratings, Tokyo, Japan, 2012; [2] - Extensively long high aspect ratio gold analyzer gratings: A. E., Hollowell, C. L. Arrington, J. J. Coleman, P. S. Finnegan, A. M. Rowen, and A. L. Dagel, X-ray and Neutron Phase Imaging with Gratings, Bethesda, MD, 2015 [3] – Double Sided Grating Fabrication for High Energy X-Ray Phase Contrast Imaging: A. E. Hollowell, C. L. Arrington, P. Finnegan, K. Musick, P. Resnick, S. Volk, and A. L. Dagel, Material Science in Semiconductor Processing, 2018, under review. Figure 1

Expected Failures in 3-D Technology and Related Failure Analysis Challenges

After an introduction to 3-D technology, and through silicon via (TSV)- and stacking options, this paper provides an overview of failures that can be expected in 3-D technology and lists the potential failure analysis (FA) techniques that can be applied to find these failures and the related challenges. Various failure mechanisms and effects that can be expected in TSVs, such as Cu pumping, voids, liner/barrier breakdown, electromigration, mechanical stress impact, Cu diffusion, plasma-induced damage, and the keep-out-zone, are discussed. Also, failures due to backside processing (thinning-induced damage, charging, and Cu exposure) and stacking (misalignment, voids, solder squeeze-out, electrostatic discharge, stress-induced cracking, and delamination) are listed. The importance of mechanical stress and chip–package interaction as a main threat for failures in 3-D technology is highlighted. The FA techniques are not discussed in detail (references are provided). There is a clear need for techniques that can detect failures, such as small (micrometer and submicrometer range) cracks, voids, and delaminated regions (both planar and vertical).

Development and adhesion characterization of a silicon wafer for temporary bonding

The development of a silicon temporary carrier for thin wafer handling for 3D applications was investigated. Process selection and optimization ended up with a silicon carrier entirely covered with an antistick layer based on a fluorinated polymer. The carrier preparation was quite easy because only one coating was used and no sticking edge zone was needed onto the carrier. The fluorinated coating led to a very hydrophobic behavior. When bonded with a thermoplastic glue, it also exhibited very antiadhesive properties because the adherence was as low as 0.4J/m2 and lower than the adherence of a stack without any antiadhesive layer (above 4J/m2). The carrier was nevertheless suitable for different back side processes in 300mm: grinding, chemical cleaning, chemical mechanical polishing and silicon oxide deposition. Compared with a commercial carrier, it exhibited the same level of performance for the integration. The proposed carrier was compatible with a mechanical debonding of a thinned bonded structure with a silicon device wafer of 80µm. The carrier recycling was possible without any new preparation.