Feasibility Study of Wafer-Level Backside Process for InP-Based ICs

Abstract

This paper reports wafer-level backside process technology, established with the intent to ensure stable operation of InP ICs in the submillimeter wavelength band, which generally suffer from ground bounce and substrate resonance. Our process consists of thinning a 3-in InP wafer, forming dense vias with interval cooling steps, backside metallization with single-level wiring and crack-free dicing. We investigate the effects of the backside process on InP-based heterojunction bipolar transistors and high electron mobility transistors. The results show that the backside process contributes to stable operation up to the 300-GHz range without any degradation of transistor characteristics.