Backside Of Wafer Research Articles

Dye‐Sensitized Back‐Contact Solar Cells

sensitized solar cells (DSCs), [ 2 ] are based on low-cost materials and can be fabricated by means of simple printing techniques. Two transparent fl uorine-doped tin oxide (FTO) coated glass substrates are conventionally used as collecting electrodes to extract photogenerated charge carriers from the dye-sensitized junction. These substrates account for a major fraction of the fabrication costs while also compromising the DSC performance due to their limited transmission and conductivity. Here, we demonstrate that back-contact solar cell confi gurations, successfully developed to increase the performance of silicon solar cells, can be used to address these limitations. For the fi rst time, we report the successful fabrication of a monolithic back-contact dye-sensitized solar cell (BC-DSC) based on an array of two interdigitated fi nger electrodes located on one common substrate. In photovoltaic cells, light absorption results in the generation of charge carriers of opposite sign, which are subsequently collected by two charge selective contacts. For silicon solar cells, [ 1 ] as well as for dye-sensitized solar cells (DCSs) [ 2 ] those collecting electrodes are most commonly located on opposite sides of the junction in a co-planar arrangement, above and below the photoactive junction. Consequently at least one of the electrodes needs to combine transparent and conducting properties, compromising both, optical transmission as well as electrical conductivity. Placing both collecting electrodes onto one common face of the photovoltaic junction provides the opportunity to use opaque electrode materials and to illuminate the junction through the opposite, optically unobstructed face. Such back-contact concepts have successfully been applied to increase the performance of silicon solar cells. [ 3 ] Charge collection in these devices is facilitated by a set of two interdigitated fi nger electrodes, co-located on the backside of the silicon wafer. [ 3 ] In this work we use analogue concepts to construct dye-sensitized back-contact solar cells that use interdigitated electrodes to effi ciently extract photogenerated positive and negative charge carries from an overlying dye-sensitized heterojunction. The potential advantages of BC-DSCs over conventional DSCs are that (1) optical transmission losses can be avoided, (2) highly conductive electrode materials can be used for charge collection, (3) opaque substrate materials can be applied, and (4) auxiliary wiring and interconnections can be integrated onto one common substrate to facilitate the fabrication of interconnected solar cell modules and their integration into electronic circuits. The most common DSC device confi guration is schematically shown in Figure 1a . The DSC electrodes consist of an FTO glass plate coated with a dye-sensitized mesoporous TiO 2 layer and an additional platinized FTO substrate sandwiched together. The cell gap is fi with an electrolyte solution that contains a redox couple such as iodide/triodide. An appropriate spacer thickness ensures that direct contact of the mesoporous TiO 2 and the opposing platinized FTO glass (counter electrode) is avoided. Dye excitation by visible light is generally followed by ultrafast electron injection into the semiconductor electrode (TiO 2 ). These photogenerated electrons show free diffusion

Journey Toward Process Convergence in TSV Technology

Continuous demand for more advanced electronic devices with higher functionality and superior performance in smaller packages is driving the semiconductor industry to develop new and more advanced 3D wafer-level interconnect technologies involving TSVs (through-silicon vias). The TSVs are created either on full-thickness wafer from the wafer front-side ¡V as part of wafer-fab processing during Middle-Of-Line (¡§via middle¡¨) or Back-End-Of-Line (¡§via last BEOL¡¨) ¡V or from the wafer backside after wafer thinning (¡§via last backside¡¨). Independent of the specific approach, the main steps include via etching, lining with insulator, copper barrier/seed deposition, via fill, and chemical mechanical planarization (CMP). Over the past year, the industry has been converging toward some primary unit processes and integration schemes for creating the TSVs. A common cost-of-ownership framework has also begun to emerge. Active collaboration underway among equipment suppliers, materials providers and end users is bringing about rapid development and validation of cost-effective TSV technology in end products. This presentation will address unit-process and integration challenges of TSV fabrication in the context of 20x100ƒÝm and 5x50ƒÝm baseline process flows at Applied Materials. Highlights of wafer-backside process integration involving wafers bonded to silicon or glass carriers will also be discussed.

Via Last using Polymer Liners and their Reliability

This paper discusses the use of polymer dielectrics as insulating liner for realizing two types of 3D-WLP through Si vias (TSV's) in Si wafers with a thickness of respectively 50 and 100μm. These TSV technologies are based on thinning first, via last approach where 3D interconnects are implemented on the backside of thinned IC fabricated device wafers. Key aspects of the TSV processes are: i) fabricating the TSV from the backside of the wafer and contacting to BEOL M1, hence it is independent of the BEOL interconnect stack. ii) use of thick polymer as via isolation is a differentiator from most classical approaches using thin CVD oxide or nitride. The result is a significantly reduced capacitance, and hence, improvement of electrical performance. Another advantage of using thick polymer is that it can absorb some of the stress induced by CTE mismatch between the Cu in via and surrounding Si. This paper presents IMEC's 3D-WLP TSV flavors developed using spin-on dielectric polymers as isolation layer and the reliability of these TSVs' while undergoing thermal cycle tests. For each wafer thickness a 3-mask process sequence is implemented to fabricate the TSVs. Different process flows are used for the different Si thicknesses. For the 100μm thick substrate, a low aspect ratio TSV is used. A Si-via is etched from the wafer backside with a bottom diameter of about 70μm. The top side of the via is chamfered and has a top diameter of about 100μm. As a dielectric liner, a photo-sensitive spin-on polymer is conformally coated on the wafer. At the via bottom, a contact hole with approximately 30μm diameter is realized by photo patterning. Next, conformal Cu plating is used as TSV metallization. For the 50μm thick substrates, a different approach is used enabling a higher aspect ratio TSV. First, a 5μm wide ring trench is etched in the Si. Subsequently, these trenches are filled with a spin-on polymer. After filling the ring trenches, the central Si pillar is etched out of the via (second litho step) and the oxide at the via bottom is removed to provide access to the lowest chip metal level. Next, bottom-up Cu via fill is used to form the TSV metallization. This via has a Cu TSV diameter of 25μm, and an overall diameter with isolation of 35μm [1]. All processes employed in the fabrication of the TSVs are performed at low temperature (<200°C) for maximum post CMOS compatibility The test vehicle used to develop the TSV technologies include TSV daisy chains of various lengths connecting different number of vias to determine the TSV yield and resistance. For both TSV approaches, yielding electrical measurements are done on fabricated TSV wafers. For 50μm thick silicon, up to 95% electrical yield is achieved and the single TSV resistance is measured to be ~10–15mΩ on bonded stacks through Kelvin structures. Thermal cycling from −40 to +125°C of TSV dies are also done, and after 1000 thermal cycles no electrical failure is observed. For 100μm thick silicon TSV approach, single TSV resistance is measured to be ~4–20mΩ with good yield. Test die are subjected to 1000 thermal cycles and results show limited yield loss.

A New Non-PRM Bumping Process by Electroplating on Si Die for Three Dimensional Packaging

A new bumping process on a Si die by electroplating without a photo-resist-mold (PRM) was assessed for the three dimensional (3D) stacking of Si dice. In this process, solder bumps were deposited selectively onto the surface of a Cu plugged-through silicon-via (TSV) in a Si die. Since lithography related processes to make a PRM for solder bumping were omitted, it can reduce the production time and cost for bumping. The substrate was a Si wafer, and TSVs were produced by deep-ion-reactive-etching (DRIE). As an insulation layer, SiO2 was formed by high-density-plasma-chemical-vapor-deposition (HDPCVD) or wet oxidation method. A Ti adhesion and an Au seed layers were deposited by sputtering. Cu was plugged into the vias by pulsed direct-current (DC) electroplating. The backside of the Si wafer was ground by chemicalmechanical-polishing (CMP). Sn bumps were electroplated on the Cu plugged vias by a current supplied through a Cu-overplated layer (COL) on the vias surface. As experimental results, wet oxidation provided a uniform SiO2 thickness through the via depth, whereas the SiO2 thickness by HDPCVD decreased with the via depth. The Ti and Au thicknesses also decreased along the via depth. In electroplating for Cu plugging,

Silicon Micro-Fabrication Technologies for Micro-Filters

Silicon micro-fabrication techniques allow for the development of microfluidic systems with very accurate control of size and uniformity of structures. In this paper we report on the silicon fabrication process of micro-filters for versatile application in fluidics systems. Micro-filters are composed of an ordered array of pillars and supply channels. Depending on pillar pitch, they can be used for, e.g., electrophoresis, chromatography and purification of biological mixtures. In this paper we focus on high performance liquid chromatography. The process that we have developed for micropillar fabrication consists of defining first 1μm diameter pillars with an inter-pillar distance of 1μm or less in an oxide hard mask with a DUV stepper, stitching is used to form few cm long patterns across the 200mm wafers. Second, the supply channels are defined with 1× alignment lithography. After definition of supply channels, deep reactive ion etching of silicon is performed with an optimised recipe to etch submicron pillars and supply channels of 100μm wide at the same time. The simultaneous etch of both structures avoids complex lithography steps otherwise necessary to protect the pillars while etching the supply channels or vice versa as would be done conventionally. Wafers are then anodically bonded to 200mm Pyrex wafers in order to seal the channels. Pyrex wafer also allows the use of optical detection system. Feed through holes for accessing the supply channels are etched on the backside of Si wafer. Filter characterization has been performed: a plate height of 1μm was measured and successful separation of 3 coumarin dyes is achieved.

A Review of Wafer Coating Methods for 3D Packaging

For many years, Front End of Line (FEOL) wafer fabrication, has used spin coating as the method of choice for photoresist application. Today, 3D packaging requires coatings applied to the non-active side of the wafer. Popular applications for back side coatings are, temporary adhesives to hold wafers to carriers during Through Silicon Via (TSV) fabrication, applying die / wafer bonding materials, and dielectric layers. Spin coating of wafers can be used to apply a number of materials for backside coatings. Although this application method is quite fast, it has a number of drawbacks which include high material waste and its limitation to low viscosity materials. Wafer Backside Coating (WBC) adhesives applied prior to dicing poses some unique challenges due to their filler loadings, and therefore the formulations can be limited by the spinning process. Today, most companies using spin coating to apply WBC materials have to lower the viscosity of the fluid with solvents, which creates other problems. Screen or stencil printing to apply WBC adhesives is a proven method and is currently in production at manufacturing sites. Screen printing gives good print uniformity, but requires a formulation that self-levels after printing. Stencil printing can be used with almost any formulation or filler loading, but is highly dependent on the tooling accuracy to maintain the coating thickness uniformity. Both methods are limited to coating thicknesses in the 25–100 micron range. There exists a need for a wafer coating methodology that can overcome the aforementioned restrictions. The ability to apply materials of varying rheologies, with low material waste and yet provide high quality, uniform coatings is required. This paper will review the current methods of applying WBC coatings. The authors will also present results from a newly developed spray coating process developed to process high viscosity fluids such as WBC coatings.

Light extraction enhancement for InGaN/GaN LED by three dimensional auto-cloned photonics crystal

Three dimensional (3-D) auto-cloned photonics crystal (APhC) of Ta2O5/SiO2 multi-layers was fabricated on the backside of the sapphire wafer that had InGaN/GaN multi-quantum well LED on the front side. 94% light extraction enhancement in comparison to the LED without APhC was obtained. Electrical properties of the LED did not altered by the APhC and its fabrication process. Experimental evidences showed that light extraction enhancement mechanism is two-folded: for rays that are emitted from the source and incident at lower angle of incidence to the APhC, the APhC acts as a high reflector; for rays incident at higher angle of incidence to the APhC, first order diffracted light from the APhC appears, the diffracted light is concentrated around the surface normal and is therefore capable of escaping.

Chirality assignment to carbon nanotubes integrated in MEMS by tilted-view transmission electron microscopy

Front side etching combined with sample tilting – instead of wafer through etching – allows for transmission electron microscopy (TEM) investigations on nanostructures integrated in microelectromechanical systems (MEMS). We present electron diffraction of an individual single-walled carbon nanotube (SWNT) suspended between sharp polycrystalline silicon tips as far as 165 μm away from the MEMS chip edge. This novel approach for transmission-beam characterization avoids complex wafer backside processing and facilitates alignment of the SWNTs to the focal plane using tips defined directly by photolithographic means. The demonstration of chirality assignment to the integrated SWNT paves the way for correlating experimentally measured response of the SWNT sensing element upon stimuli with the response predicted by theory.

Development of three-dimensional chip stacking technology using a clamped through-silicon via interconnection

This study aims at developing an advanced clamped through-silicon via (C-TSV) interconnection technology for three-dimensional (3D) chip-to-chip or chip-to-wafer packaging. The special features of the C-TSV technology include (1) the proposal of metal caps on the pads of the chip to form a nearly symmetric double-side-metal-cap structure that firmly clamps the vias on the chip, (2) the employment of a temporary conductive layer on the active side of the wafer as a seed metal layer during the electro-plating of metal caps, and (3) the introduction of a “via first redistribution” (VFR) concept in the C-TSV process for heterogeneous 3D integration and maximal performance. Basically, the metal caps can act as a bonding layer for 3D chip stacking and also a protection stopper for backside drilling. The blind vias are created using a proven low-cost laser drilling process through the wafer backside with a laminated insulation layer on the via-hole wall. Unlike the typical TSV process, the present technology has no need to carry out the seed layer deposition and photo processes to facilitate the via-hole filling with metal through electro-plating, thus being more cost-effective. Besides, because of the structural symmetry and also the tightly-clamped via structure, it can potentially yield better bonding reliability for stacked chip bonding. To demonstrate the effectiveness of the C-TSV structure for wafer-level 3D integration, feasibility study of the implementation of the novel process and mechanics comparisons of these two 3D chip stacking structures under thermal loading through finite element (FE) stress simulation are made. At last, both the thermal humidity (TH) test of 85 °C/85%RH and the 288 °C solder dipping test are carried out to demonstrate the interconnect reliability and the interface quality of the 3D interconnect technology.

Tilted-view transmission electron microscopy-access for chirality assignment to carbon nanotubes integrated in MEMS

Front side etching in combination with sample tilting – instead of wafer through etching – allows for transmission electron microscopy (TEM) investigations on nanostructures integrated in microelectromechanical systems (MEMS). We present electron diffraction (ED) of an individual single-walled carbon nanotube (SWNT) suspended between sharp polysilicon tips on the bulk of a MEMS chip. This novel approach for transmission beam characterization avoids complex wafer backside processing while allowing for chirality assignment to the integrated functional SWNT, as demonstrated here.

The low cost multicrystalline silicon solar cells

This paper presents a new solar-cell structure obtained by the front-surface texturization of multicrystalline silicon substrate by laboratory technology and main equipments used in characterization of such devices. The structure consists of an antireflection coating, a silicon active layer, front and back wafer contacts. The main objective was the minimizing the production cost maintaining the device performances. For these reasons the general technology cycle consists of maximum seven steps, a multicrystalline silicon substrate was used, the doping profile was optimized by simulations, the front-surface solar cell was texturized in order to reduce the light reflectivity and the wafer back-side was p+-diffused in order to get low series resistance. The performed measurements were in good agreement with simulations and expected results.

Alkaline Hydroxide Induced High Level of Alkali Metal Concentration Effect on the Characteristics of LTO Layer

The control and evaluations of alkali metal such as Na have been important issues in device process. LTO layer was deposited on backside of wafer as backseal of epitaxial substrate. The backseal wafer with LTO was evaluated to study effect of Na contamination which was observed after NaOH mixture dip. We found Na out diffusion from LTO layer inducing surface oxidation rate increase in oxidation process. These phenomena considered to Na property of low boiling temperature point. However, Na from LTO layer did not affect epitaxial process because of hydrogen pre-baking in epitaxy process.

Studies of Wafer Backside Micro-arcing Prevention In Encore Ta Process

In advance Cu BEOL process, Encore Ta/TaN deposition process is widely used for barrier layer deposition to achieve lower via resistance and better electro migration and stress migration performance. However, wafer micro arcing existed frequently due to complex chamber design and DC/RF/AC/ESC adoption in Encore Ta process. To solve the micro arcing issue is the one of key topics in Encore Ta process. In this study, the formation mechanism of micro arcing is analyzed. Gas plug is introduced into Encore Ta process to prevent micro arcing.

4H-SiC Schottky Barrier Diodes Using Mo-, Ti- and Ni-Based Contacts

We have studied different Schottky and ohmic contacts on 4H-SiC with the aim to obtain Schottky barrier diodes (SBDs) capable to operate at high temperatures, frequencies and power densities for long periods of time, and showing low power losses. The control of the Schottky barrier plays an important role in minimizing the power loss of a SBD, and the metal-semiconductor interface properties strongly affect the overall performances of such a device. Schottky contacts were deposited using Ni, Ti, Ti/Al, Mo and Mo/Al layers, and the annealing treatments have been performed up to 600 °C using a rapid thermal annealing process (RTA). Ohmic contacts have been deposited on the wafer backside using Ti/Al or Ti/Ni/Ag layers. The Schottky diodes have been characterized by means of standard current-voltage (I-V) and capacitance-voltage (C-V) techniques. Schottky diodes with Mo and Mo/Al barriers show a lower barrier height and better overall performances in forward polarization when compared to the Ti- and Ni-based contacts.

A low-cost through via interconnection for ISM WLP

Wafer level packaging (WLP) for image sensor device has the advantage of small size, high performance and low cost. In WLP technology, in order to form electrical interconnection from image sensor contact pad to the backside of the wafer, several structures have been developed, such as T-contact and through silicon via (TSV). In this paper, a wafer level package of image sensor with new type TSV electrical interconnection for image sensor pad is presented. The target of this development is to reduce process cost and difficulty, and increase yield of image sensor packaging. Key fabrication processes includes glass protecting wafer bonding, device wafer thinning, backside through via etching, via passivation layer deposition, pad oxide opening, via filling and backside re-routing layer formation, etc. Compared to large opening area of tapered via on the backside of CMOS image sensor wafer, only small opening area is need for making via interconnection with vertical sidewall presented in this paper. A fillet structure at bottom corner of via holes can help to reduce sequent process difficulty, so that low-cost and simplified unit processes are successfully adopted in the fabrication process for through via formation. The through via interconnection shows good electrical connection performance, and high-quality photo images are obtained by packaged image sensor device.

Failure Analysis and Process Improvement for Through Silicon Via Interconnects

AbstractThis paper investigates the failure causes for slopped through silicon vias (TSV) and presents process improvement for implementing the slopped TSV for 3D wafer level packaging (WLP). IMEC is developing slopped and scaled generic approaches for 3D WLP. Previously we have reported on the integrated process flow for the slopped (TSV) and showed the feasibility of Parylene N as a dielectric material. In the TSV process discussed here, firstly 200mm device wafer is bonded facedown on a carrier using temporary glue layer and thinned by grinding. TSV's are realized by dry etching from the wafer backside, followed by dielectric deposition and patterning. Dielectric patterning is done at the bottom of the via on 100 microns thin silicon device wafer supported by the carrier. Finally, conformal plating is done inside the via to obtain the interconnections.This paper discusses the yield killer or failure causes in the slopped TSV process. There can be many parameter including silicon etch uniformity, dielectric etching at the bottom of the via and resist residue inside the via that can reduce the yield of the process. We report that one of the main factors contributing to the yield loss is silicon dry etching effects including non-uniformity and notching. Using standard Bosch etching process, notching at the interface between landing oxide and silicon has been observed. The notching cause a discontinuity at the bottom of the via resulting in no plating at the bottom interface.In this paper we report on a new via shape that is a combination of slopped and straight etching sequence to overcome the notching problem. Different parameters including influence of grinding marks, mask opening, wafer thickness variation, etching rate and etching profile across the wafer were investigated. The optimized design rules for mask opening and effect of individual etching parameters on the etching profile will be presented. In etching, firstly a sloped via with slope of 60 degrees is optimized with changing different etching parameters including different gasses and pressure. Slope via facilitates in subsequent dielectric deposition and sputtering processes. Secondly, a straight wall etching process based on Bosch process and soft landing step with longer passivation steps were investigated to obtain the notch free etching profile. The optimized etching process is notch free, very repeatable and total variation across different wafers is less then 2 percent for 100 micron target opening.This paper reports the failure analysis of TSV and discuses the processes improvement to obtain higher yielding vias. Different parameters that reduced the yield are discussed with main focus on notching effects during silicon etching. An improved and characterized, notch free uniform silicon etching across the wafer process based on two step etching is presented. An integration flow implementing the above optimized parameters with electrical yield will be detailed in the paper.

Trace Metallic Contamination Analysis on Wafer Edge and Bevel by TXRF and VPD-TXRF

In the semiconductor industry, the edge exclusion of processed wafers is decreasing to accommodate more integrated circuits. With this trend, there is a higher risk of detrimental contamination at the wafer edge and bevel making the monitoring for metallic contamination in these areas critical. Cross contamination from the edge and bevel can occur at many processing steps. For example, metals can spread from the wafer edge, bevel and backside to the wafer’s surface in a wet cleans process. In immersion lithography, the water drop that is scanned across the wafer could transport contamination from the edge and deposit it across the wafer surface. Contamination on wafer edge and bevel can have many origins; handling systems in every process tool, reaction products in etching, and residuals of new materials in high-k for CVD and PVD, for example. To know what metallic contamination is present, and to investigate the causes are essential for wafer edge control.

Imaging of contamination on wafers using a scanning surface potential difference measurement technique

The sensitivity of the ChemetriQ ® method toward various contaminants was evaluated. Offering high resolution mapping without edge exclusion, the method based on surface work function lateral non-uniformities, i.e. the so called surface potential difference imaging (SPDI), appears to be very sensitive to traces of metals on Si wafers with native oxide. Using intentional contamination protocols and comparative methods such as total-reflection X-ray fluorescence (TXRF), different dynamics have been seen element to element. As an example, the signal for Fe and Cu contamination on Si is very strong, offering the capability to detect levels in the 10 10 at/cm 2 range, while it is in the 10 12 at/cm 2 range for Al. This does not obviously agree with work function differences between Si and the metals; and the exact reason for signal variations must be further investigated. Practical results show that the method can be applied indifferently to CZ wafer front side or backside, whatever the polish finish; can be applied to silicon on insulator (SOI) wafers; and can be very useful for the control of wafer edge contamination left after deposition and further bevel and edge etch steps.

Backside Nickel Based Ohmic Contacts to n-Type Silicon Carbide

This work focuses on Ni ohmic contacts to the C-face (backside) of n-type 4H-SiC substrates. Low-resistive ohmic contacts to the wafer backside are important especially for vertical power devices. Ni contacts were deposited using E-beam evaporation and annealed at different temperatures (700-1050 °C) in RTP to obtain optimum conditions for forming low resistive ohmic contacts. Our results indicate that 1 min annealing at temperatures between 950 and 1000 °C provides high quality ohmic contacts with a contact resistivity of 2.3x10-5 Ωcm2. Also our XRD results show that different Ni silicide phases appear in this annealing temperature range.

Effective Crosstalk Isolation With Post-CMOS Selectively Grown Porous Silicon Technique for Radio Frequency System-on-Chip (SOC) Applications

In this letter, post-CMOS substrate selective-transformation engineering based on the selectively grown porous silicon (SGPS) technique is demonstrated to effectively suppress substrate crosstalk. The testing structures for crosstalk isolation are fabricated in a standard 0.18-mum CMOS process, and porous silicon trenches are selectively grown after processing from the backside of the silicon wafer. For a testing structure with 250-mum separation on Si, a 42.8-dB improvement (from -23.5 to -66.3 dB) for crosstalk isolation is achieved at 2 GHz. The characteristics of the SGPS substrate have been extracted using the conventional lump element model, which shows that our SGPS technique increases the substrate impedance by one order of magnitude. These results demonstrate that our post-CMOS substrate selective-transformation engineering is very promising for radio frequency system-on-chip applications.