Journey Toward Process Convergence in TSV Technology

Abstract

Continuous demand for more advanced electronic devices with higher functionality and superior performance in smaller packages is driving the semiconductor industry to develop new and more advanced 3D wafer-level interconnect technologies involving TSVs (through-silicon vias). The TSVs are created either on full-thickness wafer from the wafer front-side ¡V as part of wafer-fab processing during Middle-Of-Line (¡§via middle¡¨) or Back-End-Of-Line (¡§via last BEOL¡¨) ¡V or from the wafer backside after wafer thinning (¡§via last backside¡¨). Independent of the specific approach, the main steps include via etching, lining with insulator, copper barrier/seed deposition, via fill, and chemical mechanical planarization (CMP). Over the past year, the industry has been converging toward some primary unit processes and integration schemes for creating the TSVs. A common cost-of-ownership framework has also begun to emerge. Active collaboration underway among equipment suppliers, materials providers and end users is bringing about rapid development and validation of cost-effective TSV technology in end products. This presentation will address unit-process and integration challenges of TSV fabrication in the context of 20x100ƒÝm and 5x50ƒÝm baseline process flows at Applied Materials. Highlights of wafer-backside process integration involving wafers bonded to silicon or glass carriers will also be discussed.