Back Interface States Research Articles

Low frequency noise and radiation response in the partially depleted SOI MOSFETs with ion implanted buried oxide**Project supported by the National Natural Science Foundation of China (Grant Nos. 61204112 and 61204116).

Low frequency noise behaviors of partially depleted silicon-on-insulator (PDSOI) n-channel metal-oxide semiconductors (MOS) transistors with and without ion implantation into the buried oxide are investigated in this paper. Owing to ion implantation-induced electron traps in the buried oxide and back interface states, back gate threshold voltage increases from 44.48 V to 51.47 V and sub-threshold swing increases from 2.47 V/dec to 3.37 V/dec, while electron field effect mobility decreases from 475.44 cm2/V·s to 363.65 cm2/V·s. In addition, the magnitude of normalized low frequency noise also greatly increases, which indicates that the intrinsic electronic performances are degenerated after ion implantation processing. According to carrier number fluctuation theory, the extracted flat-band voltage noise power spectral densities in the PDSOI devices with and without ion implantation are equal to 7×10−10 V2·Hz−1 and 2.7×10−8 V2·Hz−1, respectively, while the extracted average trap density in the buried oxide increases from 1.42×1017 cm−3·eV−1 to 6.16×1018 cm−3·eV−1. Based on carrier mobility fluctuation theory, the extracted average Hooge’s parameter in these devices increases from 3.92×10−5 to 1.34×10−2 after ion implantation processing. Finally, radiation responses in the PDSOI devices are investigated. Owing to radiation-induced positive buried oxide trapped charges, back gate threshold voltage decreases with the increase of the total dose. After radiation reaches up to a total dose of 1 M·rad(si), the shifts of back gate threshold voltage in the SOI devices with and without ion implantation are −10.82 V and −31.84 V, respectively. The low frequency noise behaviors in these devices before and after radiation are also compared and discussed.

Effects of back interface trap states on the fully depleted strained-silicon-on-insulator capacitorless single transistor dynamic random access memory cells

A series of systematic experiments were carried out to investigate the effects of silicon back interface state density between silicon channel layer and buried oxide layer on the memory characteristics. The back interface states of fully depleted strained-silicon-on-insulator (FD sSOI) substrate were intentionally generated by controlling the temperature of rapid thermal annealing (RTA) process and the amount of back interface trap was evaluated by using the backgated metal-oxide-semiconductor field-effect transistor method. As a result, the trap density of back interface increased with RTA temperature, which causes the degradation of FD sSOI single transistor dynamic random access memory.

Characterization of the Back Interface in Strained-Silicon-on-Insulator Channel and Enhancement of Electrical Properties by Heat Treatment

The electrical characteristics of thin strained-silicon-on-insulator (sSOI) wafers were evaluated, and the effects of annealing processes on the back interface states of sSOI wafers were analyzed by using the back-gated (BG) metal-oxide-semiconductor field-effect-transistor structure. The electrical characteristics of the BG MOSFET fabricated on sSOI wafers were superior to that of conventional SOI wafers. However, the rapid thermal annealing (RTA) process induced significant degradations by increasing the back interface states between the strained-Si thin channel and the buried oxide layer. On the other hand, the conventional furnace annealing process at 500degC in a nitrogen (N2) ambient was effective for reducing the RTA-induced back interface states, and the performances of the BG sSOI MOSFET annealed in N2 ambient were significantly improved.

Front and Back Channel Properties of Asymmetrical Double-Gate Polysilicon TFTs

Polycrystalline silicon thin-film transistors (TFTs) with different front- and back-gate lengths are investigated. In addition, the laser annealing process yields high-quality directional grains that enable us to orient TFT channels parallel or perpendicular to the grain boundaries. It is demonstrated that the turn-on voltage is not dependent on grain orientation, unlike the subthreshold swing and the maximum transconductance. Moreover, it is shown that double-gate TFTs are fully depleted and therefore back interface properties exert critical influence on the overall TFT electrical performance. From electrical measurements the back interface state density was estimated to reach values and it was shown that the electrical performance of the double-gate devices is highly dependent on the back-to-front gate-length ratio.

Temperature dependence of drain current hysteresis in FD and PD-SOI n-MOSFETs

The hysteresis characteristics of the drain current (ID) in FD-SOI n-MOSFETs are examined at different back gate voltage and temperature. The relationship between the hysteresis and the temperature is discussed in comparison with the result for PD-SOI n-MOSFETs, taking into account the back gate interface states. The ID hysteresis, which is defined as the difference of ID for VFG swept up and down, showed positive and negative peaks. The ID hysteresis peak height decreases with increasing temperature. Higher influence of the back interface states on the ID hysteresis for FD-SOI is observed than for PD-SOI by the comparison of the activation energies for decreasing ID hysteresis.

High‐performance top‐gate a‐Si:H TFTs for AMLCDs

AbstractHigh‐performance top‐gate hydrogenated amorphous silicon (a‐Si:H) thin‐film transistor (TFT) structures have been fabricated over a large area from plasma‐enhanced chemical vapor deposition (PECVD) materials. The electrical performances of the top‐gate a‐Si:H TFT (μFE≅0.75cm2/Vsec, VT≅3.5V, S≅0.55V/dec) are comparable to the electrical performances observed for an inverted‐staggered bottom‐gate a‐Si:H TFT. We have shown that the TFT field‐effect mobility first increases with the a‐Si:H thickness, and then decreases for thicker a‐Si:H films. This change of the electrical performances can be associated either with the variation of a‐Si:H microstructure with film thickness during the PECVD processes or a large density of TFT back interface states; it also involves the source/drain parasitic access resistances, especially for thick a‐Si:H layers.