Back-gate Bias Research Articles

A DC to 220-GHz High-Isolation SPST Switch in 22-nm FDSOI CMOS

A wideband single-pole single-throw (SPST) switch covering the dc to 220-GHz frequency range is presented in this letter. A four-element distributed topology is used to extend operation to the upper millimeter-wave band. With a combination of front-gate and back-gate biasing, unique to fully depleted silicon-on-insulator (FDSOI) MOSFETs, and enabled by the thick metal/dielectric backend of the technology, the switch achieves an insertion loss of 3.1 dB and an isolation of 37 dB at 220 GHz, as well as a peak isolation of 58 dB at 200 GHz, without deembedding the pads. A G-band variable gain low-noise amplifier featuring the SPST switch shows >50-dB gain control range, with a maximum peak gain of 9.5 dB at 190 GHz and a 3-dB bandwidth from 180 to 203 GHz.

Study of ΒΕSOI MOSFET Reconfigurable Transistor for Biosensing Application

The Back Enhanced SOI (BESOI MOSFET) is a planar reconfigurable device, which transistor type (n- or p-type) can be programed by the back-gate bias. This transistor is explored in this paper for biosensing application through numerical simulation, based on the fabricated device experimental results. The permittivity value and the charges inside the biomaterial deposited on the underlap region (between gate and source/drain contacts) influence the BESOI MOSFET drain current. The dimensions of the device were evaluated in order to optimize the sensitivity. Among the studied parameters, the underlap length was the most relevant parameter. For short underlap devices, the fringe electric field from the front gate electrode benefits the permittivity-based sensors, while long underlap length devices have a bigger sensitive area in which the charge-based sensor presented better results. Also, the n-type biased device presented higher sensitivity to positively charged materials, while the p-type biased one presented better result for negatively charged materials. The parameters optimization resulted in one order magnitude improvement of the sensitivity for the permittivity-based sensor, for both n- and p-type. As for the charge-based sensor, the optimized device presented twice as bigger sensitivity for the n-type, and at least eight times improvement for the p-type device. This fact represents an advantage of the BESOI structure as the type of the device can be chosen by the back-gate bias.

Performance comparison of RF energy harvesting rectifiers designed in CMOS FDSOI 28 nm with dynamic back gate biasing and BiCMOS 55 nm technology

AbstractA comparison between two Dickson voltage multipliers realized in two technologies, fully depleted silicon on insulator (FDSOI) 28 nm and Bipolar CMOS (BiCMOS) 55 nm is presented. The assessment is based on the I–V characteristics measurements of transistors configured as diodes; and on the measurements of one and two stages of Dickson multipliers designed for RF energy harvesting. The I–V characteristics show that FDSOI technology is profitable owing to its smaller threshold voltage (Vth), and a leakage current less than that of BiCMOS. Consequently, for the same input voltage, the output voltage acquired in FDSOI is greater than that achieved with BiCMOS. Moreover, for rectifiers designed in FDSOI, a dynamic back gate bias could be employed to enhance the performance by adjusting dynamically the Vth and the leakage current.

Back-Gate GaN Nanowire-Based FET Device for Enhancing Gas Selectivity at Room Temperature.

In this work, a TiO2-coated GaN nanowire-based back-gate field-effect transistor (FET) device was designed and implemented to address the well-known cross-sensitive nature of metal oxides. Even though a two-terminal TiO2/GaN chemiresistor is highly sensitive to NO2, it suffers from lack of selectivity toward NO2 and SO2. Here, a Si back gate with C-AlGaN as the gate dielectric was demonstrated as a tunable parameter, which enhances discrimination of these cross-sensitive gases at room temperature (20 °C). Compared to no bias, a back-gate bias resulted in a significant 60% increase in NO2 response, whereas the increase was an insignificant 10% in SO2 response. The differential change in gas response was explained with the help of a band diagram, derived from the energetics of molecular models based on density functional theory (DFT). The device geometries in this work are not optimized and are intended only for proving the concept.

Effects of BOX thickness, silicon thickness, and backgate bias on SCE of ET-SOI MOSFETs

In this work, we investigate the effect of BOX (Buried OXide) and silicon thickness on the SCE (Short-Channel Effects) of ET-SOI (Extremely Thin Silicon-on-Insulator) MOSFETs. It is found that the minimum channel length Lmin is only moderately sensitive to the BOX thickness but strongly dependent on the silicon thickness. For a given threshold voltage, the choice of gate work function in combination with the backgate bias also plays a role on Lmin. Reverse bias mitigates SCE while forward bias aggravates SCE. An empirical expression of Lmin in terms of silicon thickness is given.

Exploiting the Back-Gate Biasing Technique as a Countermeasure Against Power Analysis Attacks

Fully depleted silicon-on-insulator (FD-SOI) technology is renowned for its back-gate bias voltage controllability. It allows devices fabricated with FD-SOI technology to be optimized for low power consumption or high performance with proper back-gate biases, depending on the required application. This article proposes using the back-gate biasing technique in novel countermeasures against power analysis attacks. Theoretical explanations are discussed, and realistic differential power analysis (DPA) attacks, targeting AES-128 encryption on a 65-nm STOB 32-bit RISC-V microcontroller, are conducted to justify the proposed idea. The experimental results show that when compared with applying no bias, applying our first proposal, which involves using forward back-gate bias, not only improves the test device performance but also enhances its resistance to DPA attacks. Moreover, vulnerability to DPA attacks is kept unchanged when a reverse back-gate bias is applied to achieve low power consumption. The DPA resistance is even more vital when combining the back-gate bias technique with a lower supply voltage. The number of power traces required to retrieve the secret key successfully increases by 14.5 times in the best case. Even better DPA resistance can be obtained when the back-gate bias of the targeted microcontroller is dynamically randomized, as suggested by our second proposal of a random dynamic back-gate bias (RDBB). When RDBB is applied, the number of power traces required to retrieve the secret key successfully significantly increases by 33.4 times.

Impact of temperature counting the effect of back gate bias on the performance of extended source tunnel FET (ESTFET) with δp+ SiGe pocket layer

This work presents a comprehensive comparison of temperature affectability on extended source tunnel field effect transistor with δp+ SiGe pocket layer at the tunneling junction with and without the back gate bias. The impacts of temperature on different performance parameters, such as ON and OFF currents, subthreshold swing, threshold voltage, switching ratio, and analog/RF performance of the devices have been investigated. In addition, the effect of Gaussian distribution of trap charges on various interfaces viz. Si–HfO2, Si–SiO2, both Si–HfO2, Si–SiO2 is considered separately. It has been observed that, the effect of temperature on device OFF current is less when trap charges are considered to be present at various interfaces. At low temperature, ESTFET with back gate bias (DG-ESTFET) encounters more variations in performance parameters than without back gate bias ESTFET (SG-ESTFET) considering the presence and absence of trap charges in-between silicon and front gate oxide (Si–HfO2) interface. However, the reverse is found to be true when the trap charges are assumed to be present at the back gate oxide interface (Si–SiO2) and both the interfaces (Si–HfO2, Si–SiO2). Finally, analog/RF performance of ESTFET without back gate bias (SG-ESTFET) is found to be less affected by temperature variations.

Resistive switching behavior and mechanism of multilayer MoS<sub>2</sub> memtransistor under control of back gate bias and light illumination

Memtransistor is a new multi-terminal device which combines the properties of memristor and field effect transistor and simultaneously realizes information storage and processing. In this paper, the multilayer MoS<sub>2</sub> is prepared by micromechanical exploration method, then the back gate MoS<sub>2</sub> memtransistor with field effect transistor structure is fabricated, and the resistive switching characteristics and mechanism of the device under electric field, light field and their synergistic regulation are systematically studied. The experimental results show that the multilayer MoS<sub>2</sub> memtransistor has excellent bipolar resistance behavior and good cycle durability. Under the control of gate voltage, the switching ratio of the device can be tuned in a range of 10<sup>0</sup>－10<sup>5</sup>, up to 1.56 × 10<sup>5</sup>, which indicates that the device has a strong gating effect. Under the control of light illumination, the resistance characteristics of the device are strongly dependent on the incident wavelength. When photoelectric synergistic regulation is performed, the device displays excellent four-terminal control capability, and the switching ratio is enhanced up to 4.8 × 10<sup>4</sup>. The mechanism of resistive switching characteristics can be attributed to the changes of charge capture state and Schottky barrier height at the interface between MoS<sub>2</sub> and metal electrodes, and the continuous photoconductance effect caused by photogenerated carriers in MoS<sub>2</sub> channel.

A 28–34-GHz Stacked-FET Power Amplifier in 28-nm FD-SOI With Adaptive Back-Gate Control for Improving Linearity

Adaptive back-gate control of a stacked-FET power amplifier (PA) in 28-nm fully depleted silicon-on-insulator (FD-SOI) CMOS is demonstrated for the 64-QAM signal at 28 and 31 GHz. Adaptive bias control (ABC) is applied to the back gate to effectively enhance the linearity of PAs for wideband waveforms with up to an 800-MHz envelope frequency. Third-order intermodulation distortion (IMD3), which degrades the linearity of a PA, is improved by adjusting back-gate biases of the stacked-FET PA according to the input power level without any concerns about wideband operation. From 28 to 34 GHz, the presented PA provides P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> and PAE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P1dB</sub> of 16.4-dBm and 37.3%, respectively. At 28 and 31 GHz, the measured P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> and PAE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P1dB</sub> are 17.4 and 16.9 dBm, 37.7% and 38.8%, respectively, with a compact core area of 0.088 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The rms EVM improvement due to the linearity enhancement with the adaptive back-gate control is experimentally demonstrated to be around 2.6 and 1.8 dB for 8.65-dB PAPR single-carrier 64QAM signals with 8-dB back-off at 28 and 31 GHz, respectively.

Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies

This paper presents an analysis of the silicon film thickness (6 nm and 14 nm), the gate dielectric material (SiO2 and High- κ material) and the Ground Plane influence on the analog parameters of Ultra Thin Body and Buried Oxide (UTBB) SOl nMOSFET devices, based on experimental and simulation results. Two channel lengths (70 nm and 1μm) have been considered and the analog performance has been analyzed as a function of the back gate bias. It is shown that at zero back gate bias , the presence of a Ground Plane improves the transconductance in the saturation region due to the strong coupling between front and back gates in devices with a long channel (1 μm), thin silicon film (6 nm) and SiO2 as gate dielectric material. However, for the intrinsic voltage gain, output conductance and Early Voltage, the devices without Ground Plane present better results due to the higher drain electrical field penetration. Short-channel transistors (70 nm) with Ground Plane show an improvement of the analog parameters also due to the high drain electrical field penetration. Similar behavior is noticed in devices with a thicker silicon film (14nm). UTBB nMOSFETs with High- κ material present less influence of a Ground Plane on the parameters analyzed. Varying the back gate bias in devices with long channel (1 μm) and SiO2 as gate dielectric material, the analog parameters present better results in devices without Ground Plane, except for the transconductance in long channel transistors with a thin silicon film, for the reason explained before (strong coupling between front and back gates). Devices with High-κ material as gate dielectric show a minor improvement of the analog performance with a Ground Plane.

The Influence of Back Gate Bias on the OCTO SOI MOSFET’s Response to X-ray Radiation

This work investigates the X-ray irradiation impact on the performance of an on-conventional transistor called OCTO SOI MOSFET that adopts an octagonal gate shape instead of a rectangular. The electrical behaviors of both devices were studied through an experimental comparative analysis of the total ionizing dose influence. In addition, the back-gate bias technique was applied in these devices to reestablish its threshold voltages and drain currents conditions that were degraded due the trapping of positive charges in the buried oxide. As the main finding of this work, after the irradiation procedure, we notice that the OCTO device is capable to reestablish its pre-rad electrical behavior with a smaller back gate bias than the one observed in the standard one counterpart. This is mainly because the parasitic transistors in the bird’s beak region are practically deactivated due the particular octagonal gate geometry.

Effects of Back-Gate Bias on the Mobility and Reliability of Junction-Less FDSOI Transistors for 3-D Sequential Integration

Low thermal budget junction-less transistors with back-gate are fabricated as top-tier devices for 3-D sequential integration. The impact of back-gate bias on carrier mobility and bias temperature instability (BTI) reliability is investigated. The back-gate bias is shown to modulate the carrier mobility: specifically, mobility is increased under forward back-gate bias (FBB), which is ascribed to the carrier redistribution from the front-gate interface toward back-gate interface. Regarding BTI reliability, if a back-gate bias ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BG}}{)}$ </tex-math></inline-formula> is applied only during ON-state and a constant front-gate stress <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {G}}$ </tex-math></inline-formula> is used, BTI reliability is not influenced by the applied <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BG}}$ </tex-math></inline-formula> (due to its negligible impact on the front-gate oxide field, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {ox}}{)}$ </tex-math></inline-formula> . Therefore, supplying an FBB during ON-state can be used to adjust device performance—as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BG}}$ </tex-math></inline-formula> modulates the channel current through <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {th}}$ </tex-math></inline-formula> and mobility—without reliability penalty. On the other hand, if the back-gate bias is applied during both ON- and OFF-states, while a constant stress <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {ov}}$ </tex-math></inline-formula> is maintained by adjusting the front-gate <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {G}}$ </tex-math></inline-formula> [i.e., <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {G}}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {th}}{(}{V}_{\text {BG}}{)}$ </tex-math></inline-formula> is kept constant under different <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BG}}$ </tex-math></inline-formula> ’s], the BTI reliability can be improved under FBB (due to a reduced <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {ox}}$ </tex-math></inline-formula> in the front-gate) without performance loss. The latter property can be used to improve the device reliability under circuit operation.

Controlling the Effective Channel Thickness of Junctionless Transistors by Substrate Bias

Substrate-bias-affected unique electrical characteristics of junctionless transistors (JLTs) were investigated in detail. Bulk channel thickness of JLTs (t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">si_eff</sub> ) was effectively modulated by back-gate bias (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gb</sub> ). The variation in threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) and mobility degradation were observed in the reduced t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">si_eff</sub> , due to the negative V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gb</sub> -induced depletion of free electrons. The V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gb</sub> effect was also influenced significantly by the doping concentration in JLTs. In addition, numerical simulations verified those results and analytical equations explained well the experimental results.

A New Simulation Approach of Transient Response to Enhance the Selectivity and Sensitivity in Tunneling Field Effect Transistor-Based Biosensor

In this work, a new simulation approach of transient analysis on single cavity dielectric-modulated (DM) p -type of tunnel field-effect transistor (TFET) is examined for biosensing applications. The device operation and performance are investigated using the 2D device simulator and results are well-calibrated with experimental data. In this work, we have examined DC transfer characteristics, the transient response of drain current, drain current sensitivity (S), and selectivity (AS). Focussing more on the transient results, we have obtained maximum sensitivity of orders greater than 108 for APTES biomolecule with respect to air and a significant selectivity value in orders of 103 for APTES with respect to Biotin biomolecule. The performance of the device in terms of selectivity can be further improved (~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> ) by optimizing the back-gate bias, and therefore, the impact of back-gate bias has been analysed. The results for charged biomolecules and partially filled cavity are further investigated & highlighted. The DM p-TFET biosensor shows a significant improvement in the results with the transient response for biosensing applications with the feasibility of operating at low voltages (gate voltage of -2.0 V, drain voltage of -0.5 V and back gate voltage 0 to 0.5 V).

Investigation on the Effects of Substrate, Back-Gate Bias and Front-Gate Engineering on the Performance of DMTFET-Based Biosensors

In this work, the performance of a Double-Gated Silicon on Insulator (DG-SOI) Dielectrically Modulated Tunnel Field Effect Transistor (DMTFET) architecture is systematically investigated for label-free bio-sensing applications with the help of extensive device-level simulations. In this context, the effects of bulk oxide (BOX) substrate and back-gate biasing are emphasized and analyzed from the cavity and channel electrostatics and Band to Band Tunneling (BTBT) component of DMTFET. It is found that the electrostatic coupling between BOX substrate and channel significantly degrades the sensing performance of DG-SOI DMTFETs, whereas an applied negative back-gate bias enhances the performance of such transducer. In this line, a dual metal (DM) gate architecture is introduced that can effectively enhance the influence of applied back-gate bias and thereby leads to sensitivity improvement from 10% to 110% in DM DG-SOI DMTFET depending on bio-molecule sample specifications. Furthermore, it is observed that for suitable applied back-gate bias, the interface trap-state induced variations in sensitivity of DG-SOI DMTFETs can be reduced by even an order of magnitude. Finally, a comparative sensing performance study of proposed DMTFET with their reported counterparts establishes the advantage of such biosensors for bio-molecules with smaller dielectric constant. A similar study also shows the superiority of the proposed DMTFET over its MOSFET counterpart for wide bio-molecular sample specifications.

TID Response of Nanowire Field-Effect Transistors: Impact of the Back-Gate Bias

The impact of back-gate bias on the total ionizing dose (TID) response of silicon-on-insulator (SOI) nanowire field-effect transistors (NWFETs) is investigated. The voltage shift induced by TID is studied using different NWFET geometries and as function of the bias applied to the back-gate made of the silicon substrate. Modifications induced on static electrical characteristics, that is, drain current versus gate-to-source voltage $I_{\mathrm {D}}(V_{\mathrm {GS}})$ characteristics, are investigated. Experimental results highlight that the bias applied to the back-gate during $I{-}V$ measurements strongly impacts the NWFET TID response. At 0 V applied to the back-gate, a usual TID behavior is observed. $I{-}V$ curves are shifted to negative $V_{\mathrm {GS}}$ values, which is consistent with the literature. In contrast, two competing mechanisms are shown when negative biases are applied to the back-gate. $I_{\mathrm {D}}(V_{\mathrm {GS}})$ curves are first shifted to positive $V_{\mathrm {GS}}$ values for low TID before showing a more usual negative TID-induced voltage shifts. This two-step behavior may be attributed to several phenomena. They include either a modification of the net trapped charge sign for several back-gate biases and/or a motion of carriers trapped into the Buried OXide (BOX). The major goal of this article is to identify the mechanism at stake which drives this combined TID/electrostatic behavior.

High-mobility junction field-effect transistor via graphene/MoS2 heterointerface

Monolayer molybdenum disulfide (MoS2) possesses a desirable direct bandgap with moderate carrier mobility, whereas graphene (Gr) exhibits a zero bandgap and excellent carrier mobility. Numerous approaches have been suggested for concomitantly realizing high on/off current ratio and high carrier mobility in field-effect transistors, but little is known to date about the effect of two-dimensional layered materials. Herein, we propose a Gr/MoS2 heterojunction platform, i.e., junction field-effect transistor (JFET), that enhances the carrier mobility by a factor of ~ 10 (~ 100 cm2 V−1 s−1) compared to that of monolayer MoS2, while retaining a high on/off current ratio of ~ 108 at room temperature. The Fermi level of Gr can be tuned by the wide back-gate bias (VBG) to modulate the effective Schottky barrier height (SBH) at the Gr/MoS2 heterointerface from 528 meV (n-MoS2/p-Gr) to 116 meV (n-MoS2/n-Gr), consequently enhancing the carrier mobility. The double humps in the transconductance derivative profile clearly reveal the carrier transport mechanism of Gr/MoS2, where the barrier height is controlled by electrostatic doping.

Gate controllable spin transistor with semiconducting tunneling barrier

In this work, we have fabricated a single layer graphene spin transistor on SiO2/Si with a semiconducting tri-layer MoS2 as the tunneling barrier between the ferromagnetic electrodes and the graphene channel. The spin transport in this parallel heterostructure were investigated in detail. The spin switch signal was controlled by tuning the conductivity of MoS2 with different gate voltages. When MoS2 was turned off under negative back gate voltage, the spin switch signal was clearly obtained, whereas it disappeared when MoS2 was conductive under positive back gate bias. This spin transistor showed on, subthreshold and off states when back gate voltage changed from negative to positive. This work exploited a new possibility of semiconducting 2D materials as the tunneling barrier of spin valves.

Investigation the impact of the gate work-function and biases on the sensing metrics of TFET based biosensors

In this work, we examined the impact of gate work-function and back-gate bias to enhance sensing metrics of a Dielectric Modulated (DM) p-type Tunnel Field Effect Transistor (p-TFET) based biosensor. The sensing metrics, namely Sensitivity (S) and Selectivity (ΔS) are considerably improved by using a lower value of gate work-function and positive back gate voltages. It is shown that by appropriate selection of gate work-function and back gate bias, Band-to-Band Tunneling (BTBT) of carriers is reduced and a significant change in electrical characteristics is observed in a device with an empty cavity. Therefore, the relative change in the drain current due to the presence of biomolecules in the nanogap cavity is maximized. Results indicate a Sensitivity of ∼109 for 3-aminopropyltriethoxysilane (APTES) biomolecule, and Selectivity of ∼102 for APTES concerning Biotin biomolecule in an optimally designed p-TFET biosensor. The impact of location, as well as the charge of biomolecules, are also analyzed in this work. Results showcase the additional degree of freedom through device optimization which facilitates the tunability of sensing metrics for improved biosensor performance.

Substrate Effect Evaluation by the Analysis of Intrinsic Capacitances in SOI UTBB Transistors

The main goal of this paper is to present the behavior of the substrate effect in Ultra-Thin Body and Buried Oxide (UTBB) SOI MOSFETs with respect to the back gate bias (VSUB) through DC and AC simulations validated to experimental data. Different ground plane (GP) arrangements have been considered in order to enhance the analysis. It has been shown that the substrate effect is strongly influenced by the reduction of the back gate bias and, that the capacitive coupling of the structure presents a different behavior with respect of each kind of GP configuration as the back gate bias is varied. Finally, it has been shown that the GP below the source and drain regions contributes significantly to the overall capacitive coupling of the transistors.