Back Bias Research Articles

Tree rings in Large Synoptic Survey Telescope production sensors: its dependence on radius, wavelength, and back bias voltage

Tree rings are one of the sensor effects that may affect precise measurements in the Large Synoptic Survey Telescope (LSST). The effect is caused by silicon wafer manufacturing process, resulting in formation of circular patterns due to variations of the silicon dopant concentration. We have analyzed flat-field images taken at Brookhaven National Laboratory and SLAC for all production sensors used to build the LSST camera in order to measure the amplitudes and periods of the tree ring patterns as a function of the radius, illumination wavelength, and sensor back bias voltage. With nominal back bias voltage settings, the tree ring amplitudes and periods for both ITL and e2v sensors are considered to have small impact on the galaxy shear measurement in LSST.

Fabrication and pH Sensitivity Analysis of In-Situ Doped Polycrystalline Silicon Thin-Film Junctionless BioFET

In this letter, we demonstrate a low cost, CMOS compatible fabrication approach for the development of a back gate controlled, in situ -doped polysilicon junctionless BioFET employed for pH detection. The use of polycrystalline silicon as a device layer adds up the novelty yielding hysteresis free current characteristics. We also demonstrate the effect of gate bias on pH sensitivity evaluated in terms of relative changes in threshold voltage ( $\triangle {V}_{\text {Th}}/{V}_{\text {Th}}$ ) and maximum drain current ( $\triangle {I}_{D}/{I}_{D}$ ). At a back gate bias of 6 V, the device yields a maximum sensitivity of 92.2% and 31.7% for $\triangle {I}_{D}/{I}_{D}$ and $\triangle {V}_{\text {Th}}/{V}_{\text {Th}}$ , respectively, for pH 11.2. Further linearity of the proposed BioFET for the pH range of 3.1–11.2 is investigated at different values of ${V}_{\text {gs}}$ . The best linear fit with the error of 1.25 and 0.61 for $\triangle {I}_{D}/{I}_{D}$ and $\triangle {V}_{\text {Th}}/{V}_{\text {Th}}$ , respectively, is observed at ${V}_{\text {gs}}$ of 6 V, while ${V}_{gs}=3$ V and ${V}_{gs}= -2$ V comparatively have higher straight line fit errors of 2.03 and 1.67, respectively. The drain current of $100~\mu \text{A}$ at ${V}_{\text {ds}}={V}_{\text {gs}}=-2$ V suggests successful low-power operation of the proposed device.

16‐1: The role of hydrogen and surface potential in the performance and stability of poly‐Si TFTs on plastic substrates

In this work, we report that H in poly‐Si and surface potential in channel play a critical role in the performance and stability of LTPS TFTs. We increased H contents in poly‐Si film from 0.059 to 0.061 atom% resulting in the decrease of the fast state trap density from 4.9~5.8 × 1010/cm2 to 3.6~4.6 × 1010/cm2. Also, we increased surface potential by applying the appropriate back gate bias in TFTs, resulting in the more reduction of effective trap state density down to 1.7~2.0 × 1010/cm2. This resulted in the increase of the field effect mobility up to 115.4cm2/V·sec and decrease of hysteresis below 0.1V. We implemented these technologies into our flexible AMOLED panel.

Suppression technique of vertical leakage current in GaN-on-Si power transistors

This paper analyzes the possible physical mechanisms responsible of high vertical leakage in GaN-on-Si power transistors. Vertical leakage and back bias measurement are presented and compared against TCAD simulations with the aim of identifying the physical phenomena and parameters that impact the vertical leakage. An easy-to-implement TCAD approach for simulating the non-ideality of the AlN nucleation layer and AlN/Si interface is introduced. Finally, a method to largely suppress the vertical leakage via implantation of highly doped p++ wells at the AlN/Si interface is proposed and investigated via TCAD simulations. The suggested technique allows for a reduction of five orders of magnitude in the leakage current when a p++ surface doping in excess of 5 × 1019 cm−3 is implanted at the Si-substrate surface. In this work, a normally-on HEMT is investigated but the analysis can be extended to any GaN-on-Si power device.

1T Pixel Sensor Based on FDSOI Transistor Optical Back Biasing

This paper presents the study of a monolithically integrated FDSOI-based pixel sensor, called FDPix. The FDPix consists in cointegrating a photodiode in the substrate of an fully depleted silicon on insulator (FDSOI) transistor. Its principle of operation is based on optical back biasing of FDSOI transistor characteristics under photodiode illumination. A reset mechanism is demonstrated using the back gate of the transistor and can be applied commonly to all pixels, allowing a very small footprint. The investigation is carried out by means of TCAD simulation, analytical modeling, and optoelectrical characterization to evaluate the sensor’s characteristics and to optimize the device technological parameters. The pixel exhibits two responses, linear response at low intensities and logarithmic response at high intensities, achieving a high dynamic range (DR) of 120–130 dB.

Design and investigation of dopingless dual-gate tunneling transistor based on line tunneling

The dopingless tunneling FET (DLTFET) has attracted more and more attention due to the reduction of process complexity comparing to traditional TFET with heavy doping source and drain regions. But the on-state current of conventional DLTFET is lower because its on-state current is only determined by point tunneling (PT) between source and channel. In this work, a new dual-gate DLTFET based on line tunneling (LT) is designed and studied by Sentaurus TCAD simulation tool. The on-state current and subthreshold swing (SS) of DLTFET are greatly improved by skillfully designing back gate engineering and bias. Applying this novel design, the line tunneling is created from channel bottom to channel top, which dramatically enhances tunneling area and tunneling current. So the on-state current of LT_DLTFET consists of point tunneling between source and channel as well as line tunneling in channel region. Comparing to the traditional PT_DLTFET based on Ge, the simulation results reveal that the on-state current of LT_DLTFET based on Ge is increased to 14.8μA/μm from 6.5μA/μm at Vg=1V and Vd=0.5V, and the average SS and minimum SS are decreased to 22.9mV/dec and 6.5mV/dec from 33.9 mV/dec and 9.5mV/dec, respectively. The LT_DLTFET is also proper to both Si and III-V materials. This design greatly promotes the application potential of DLTFET.

Hole mobility in the ultra-thin-body junctionless germanium-on-insulator p-channel metal-oxide-semiconductor field-effect transistors

Junctionless Germanium-on-insulator (GOI) p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) have been realized with an ultra-thin-body (UTB) channel of down to 6 nm. The hole mobility of 166 cm2/V s has been realized at an Ns value of 1013 cm−2 attributable to the reduction of carrier scattering by interface traps under a bulk transport behavior for the devices. The back bias dependence of the hole mobility in junctionless UTB GOI pMOSFETs was examined; it is found that the hole mobility in the devices is dominated by the surface roughness scattering at the MOS interface.

Application of back bias to interdigital-electrode structured diamond UV detector showing enhanced responsivity

An interdigital electrode of 200-nm thickness, 160-μm spacing, and 160-μm width was fabricated on one side of a diamond fabricated by chemical vapor deposition. A gold contact of 200-nm thickness was deposited on the back side of the diamond. The back contact and one half of the interdigital electrode were connected by a switch. Higher responsivity and higher detectivity were observed when the back electrode contact was activated. The results of electrical field simulation showed that a stronger electrical field formed over the diamond region in the device with the back electrode than in that without the back electrode. This indicated that the detector performance improvement could be attributed to the higher carrier collection efficiency achieved with the back electrode, particularly under ultraviolet (UV) light at certain wavelengths, which have longer attenuation lengths in diamond. This structure could also be applied to UV detectors based on other wide-band-gap semiconductors.

Better Science by Beating Back Bias

Better Science by Beating Back Bias

Better Science by Beating Back Bias.

ADVERTISEMENT RETURN TO ISSUECommentNEXTBetter Science by Beating Back BiasStaci SimonichStaci SimonichMore by Staci Simonich and David L. Sedlak*David L. SedlakMore by David L. SedlakCite this: Environ. Sci. Technol. 2019, 53, 5, 2271–2272Publication Date (Web):February 21, 2019Publication History Published online21 February 2019Published inissue 5 March 2019https://doi.org/10.1021/acs.est.9b00810Copyright © 2019 American Chemical SocietyRIGHTS & PERMISSIONSArticle Views1840Altmetric-Citations-LEARN ABOUT THESE METRICSArticle Views are the COUNTER-compliant sum of full text article downloads since November 2008 (both PDF and HTML) across all institutions and individuals. These metrics are regularly updated to reflect usage leading up to the last few days.Citations are the number of other articles citing this article, calculated by Crossref and updated daily. Find more information about Crossref citation counts.The Altmetric Attention Score is a quantitative measure of the attention that a research article has received online. Clicking on the donut icon will load a page at altmetric.com with additional details about the score and the social media presence for the given article. Find more information on the Altmetric Attention Score and how the score is calculated. Share Add toView InAdd Full Text with ReferenceAdd Description ExportRISCitationCitation and abstractCitation and referencesMore Options Share onFacebookTwitterWechatLinked InReddit PDF (393 KB) Get e-AlertsSUBJECTS:Environmental science,Quality management Get e-Alerts

Mobility extraction for short channel UTBB-FDSOI MOSFETs under back bias using an accurate inversion charge density model

In this work we measure the inversion charge density for short UTBB-FDSOI MOSFETs (down to 45 nm) using an accurate method for the extraction of the parasitic components which take into account the effect of the back bias. Based on these results, we propose a modification of the inversion charge density model that uses the simplified Lambert function in order to include the back bias effect. This model is then validated with the experimental data for different gate lengths (from 185 nm to 45 nm). It is shown that this inversion charge model is valid for the mobility extraction and gives very good assessment of the mobility if we know only the IV-characteristic, the threshold voltage (under back bias effect) and the inversion charge capacitance. Finally, this method is used to extract the mobility for short channel devices (down to 40 nm) and it is found that the short channel mobility suffers from degradation even for large back biases. For the shortest device, it is demonstrated that the main source of mobility degradation is caused by oxide charges and interface states located near the S/D extensions and then it is deduced that the mobility reduction for large back biases is related to neutral defects from Si-crystal close to the channel edge.

Comparison between nMOS and pMOS Ω-gate nanowire down to 10 nm width as a function of back gate bias

This paper presents a comparison between nMOS and pMOS Ω-Gate Nanowire for different channel width (WNW) down to 10 nm as a function of the large back gate bias variation (from +20 to −20 V) experimentally and by simulation. The main digital and analog parameters are analyzed in these devices as threshold voltage, subthreshold swing (SS), transconductance, transistor efficiency, Early Voltage and intrinsic voltage gain for transistor channel width from 220 nm down to 10 nm. It is shown that narrow channel devices (WNW = 10 nm) present a small variation on the analyzed parameters as a function of back gate voltage due to stronger electrostatic control between gate and channel considering that they are effectively working like a gate-all-around devices. In general, all the nMOS parameters presents better results compared to pMOS due to the mobility enhancements. For wider devices (WNW = 220 nm), it depends on the back interface condition. For a large enough back gate bias that tends to create a back interface conduction (+20 V for nMOS and −20 V for pMOS), the SS degrades from 61 mV dec−1 (WNW = 10 nm) to 68 mV dec−1 (WNW = 220 nm). However for a large enough back gate bias that induces a non-conduction region (tends to accumulation) at back interface (−20 V for nMOS and +20 V for pMOS) the SS changes from 60 to 62 mV dec−1 at the same WNW range, which is a very acceptable results. Additionally, the drain current (ION) and transconductance (linear and saturation regions) increase for this back gate bias condition (tends to accumulation), working almost like a pseudo nanosheet device for these parameters, avoiding also the parasitic conduction at the back interface. However, in spite of the intrinsic voltage gain is almost independent of the back gate bias, it improves of at least 10 dB for narrow devices due to the higher Early voltage and almost similar transistor efficiency than the wider ones.

An SOI Photodetector With Field-Induced Embedded Diode Showing High Responsivity and Tunable Response Spectrum by Backgate

In this paper, we demonstrate experimentally a photodetector based on silicon-on-insulator substrate. The photosensing diode is formed in the substrate induced by the backgate bias instead of doping. TCAD simulation is conducted to confirm that the field-induced junction performs similarly as the doped p-n junction in terms of photodetection. A simplified process flow with low process temperature is developed to fabricate the device, which can save implantation step and reduce the cost. The photoresponses of the device under various biases, light intensities, and wavelengths are studied systematically with both experiment and TCAD simulation. Responsivity up to 1150 A/W is achieved experimentally. In addition, the response spectrum can be modulated by the back gate bias, which is a very attractive feature for multiband photodetection application. The field-induced photodiode in the substrate modulates the threshold voltage of the MOSFET at top Si layer as efficiently as the doped junction, confirmed by TCAD simulation.

Resistance-Based Modeling for Soft Errors in SOI SRAMs Caused by Radiation-Induced Potential Perturbation Under the BOX

Silicon-on-insulator (SOI) technology has been considered capable of developing devices with high tolerance against soft errors. In addition, with a thin buried oxide (BOX) layer, reduction in power consumption can be further achieved by applying a back bias from under the BOX, which is one of SOI technology’s many advantages and is appealing to Internet-of-Things and space applications. Recently, it was found during a heavy ion experiment that a static random access memory fabricated with a thin-BOX SOI technology exhibited a 100-fold soft error sensitivity when it received a back-bias. This was due to long line-type formation of multiple cell upsets (MCUs) caused by radiation-induced potential perturbation under the BOX. In this paper, a resistance-based model is developed for the evaluation of potential perturbation, predicting the device soft error sensitivity. The predictions made are verified by simulation. The model also provides an explanation to why the line-type MCU only occurs in a certain radiation environment and an optimization method to reduce the potential perturbation.

Comparison of power consumption and circuit performance between back bias in FDSOI and body bias in bulk silicon

Comparison of power consumption and circuit performance between back bias in FDSOI and body bias in bulk silicon

The total ionizing dose response of leading-edge FDSOI MOSFETs

In this paper, the total ionizing dose (TID) response of Ultra-Thin SOI (UTSOI) transistor is presented. TID experiments were performed on both NMOS and PMOS transistors under three different bias configurations (ON-state, OFF-state, TG-state). The results show that the OFF bias is relatively worse compared to other bias configurations for both NMOS and PMOS transistors. And the TID response variability caused by bias configuration during irradiation is small in UTSOI transistors. Besides this, the impact of back gate bias on TID response is also investigated. When a positive back bias is applied on NMOS transistor to achieve better performance, the threshold voltage degradation caused by TID becomes worse. While the negative back bias of PMOS transistor can lead to both better performance and higher TID tolerance. An explanation of back gate impact on front gate TID response is given with TCAD simulation.

Regaining Switching by Overcoming Single-Transistor Latch in Ge Junctionless MOSFETs

This paper reports on the suppression of single-transistor latch, an extreme condition of impact ionization (I.I.), in n-type double-gate germanium (Ge) junctionless (JL) transistors. It is shown that JL transistors can be latched to the on-state due to an increase in the I.I. generated power per unit volume with an increase in drain bias, film thickness, oxide thickness, and doping. Latch, being detrimental to switching, can be effectively suppressed by applying an appropriate negative (positive) back-gate bias for n-type (p-type) JL MOSFET. The independent gate operation with appropriate back bias allows the device to overcome latching and regain switching action with a subthreshold swing ( ${S}$ -swing) <10 mV/decade at room temperature. The work showcases the limit imposed on back bias due to an increase in off-state current due to band-to-band tunneling along with the utility of sidewall spacer to effectively suppress the same. We also show the tunability of hysteresis using back-gate bias. The work highlights a systematic methodology to eliminate single-transistor latch while preserving sub-60 mV/decade switching in Ge JL MOSFETs.

Modeling Short-Channel Effects in Asymmetric Junctionless MOSFETs With Underlap

This paper proposes a semianalytical model to estimate short-channel effects for independent gate operation in double-gate (DG) junctionless (JL) MOSFET incorporating gate-to-source/drain underlap, through the solution of Poisson’s equations in the subthreshold regime. The model also accounts for the asymmetry in device operation through variation in gate oxide thicknesses, gate work functions, and underlap lengths. Subthreshold drain current, threshold voltage, and subthreshold swing, evaluated from the channel potential, show reasonable agreement with simulation data. Results suggest the use of negative back gate bias and longer underlap length to reduce off-current. This paper highlights the role of doping, underlap length, and back gate bias in tuning the threshold voltage. This model serves as a generic formulation (within limits) with different asymmetries to estimate, design, and optimize self-aligned DG JL transistors for subthreshold logic applications.

Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs

This work proposes a new method for dissociating both channel conductions of two levels vertically stacked inversion mode nanowires (NWs) composed by a Gate-All-Around (GAA) level on top of an Ω-gate level. The proposed methodology is based on experimental measurements of the total drain current (IDS) varying the back gate bias (VB), aiming the extraction of carriers’ mobility of each level separately. The methodology consists of three main steps and accounts for VB influence on mobility. The behavior of non-stacked Ω-gate NWs are also discussed varying VB through experimental measurements and tridimensional numerical simulations in order to sustain proposed expressions of mobility dependence on VB for the bottom level of the stacked structure. Lower mobility was obtained for GAA in comparison to Ω-gate. The procedure was validated for a wide range of VB and up to 150 °C. Similar temperature dependence of mobility was observed for both Ω-gate and GAA levels.

Wafer Scale Graphene Field Effect Transistors on Thin Thermal Oxide

Graphene, an allotrope of carbon, shows ambipolar transfer characteristics with a linear dispersion relation where the conduction and valence band meets at the Dirac point 1. Owing to an absence of bandgap, it is not feasible to use graphene in logic applications though it is possible to use graphene in analog and RF circuits2. Significant efforts towards the growth and transfer of graphene onto arbitrary substrates 3 4 , 5 6 has made it feasible to scale up graphene device fabrication – early focus on single, exfoliated devices has given way to large area, many-device wafers. From a practical standpoint, a lower operating voltage range, minimal unintentional doping of graphene during processing, and excellent device stability at room temperature is required. Most of the earlier graphene based devices were fabricated on thick (90nm or higher) thermal SiO2 substrate as they provide a better optical contrast after transferring graphene. Unfortunately, this attributes to a higher operating voltage in order to modulate the graphene device. In this work, we demonstrate the feasibility of making devices on thin, 10 nm thermal SiO­2 gate dielectric using CVD graphene with minimal shift in the Dirac point and excellent stability during subsequent operation cycles in air at room temperature. The 10nm thermal SiO2 has a breakdown field of ~9.7MV/cm and mobilities as high as 2200 cm2/V·S is achieved in a relatively small operating voltage (±8V). A higher mobility is typically seen for devices located at the center of the transferred graphene region. The 10nm dielectric used in our process is challenging for integration since graphene cannot be visually inspected during device fabrication, but we have overcome this limitation by implementing specialized characterization steps that allow us to monitor the graphene. A lower contact resistivity of 500 Ω-µm and sheet resistance (RSh) of 400Ω/□ is observed at a higher doping level achieved by applying a fixed back gate bias with Ni/Au contact. A similar trend is seen in the RSh extracted from a more appropriate test structure (Van der Pauw), wherein there is a minimal metal contact overlap with graphene. The hysteresis for these graphene devices are consistently less than or equal to 0.3V within the ± 8V sweeping voltage range. Therefore, we demonstrate the fabrication of wafer scale graphene devices with excellent process control on thin dielectric substrate with minimal doping and trapped charge. This could pave way for realization of high performance, low power consuming nanoelectronics with graphene. (1) Novoselov, K. S.; Geim, A. K.; Morozov, S. V.; Jiang, D.; Zhang, Y.; Dubonos, S. V.; Grigorieva, I. V.; Firsov, A. A. Electric Field Effect in Atomically Thin Carbon Films. Science. 2004, 306, 666–669. (2) Schwierz, F. Graphene Transistors. Nat. Nano. 2010, 5, 487–496. (3) Colombo, L.; Wallace, R. M.; Ruoff, R. S. Graphene Growth and Device Integration. Proc. IEEE 2013, 101, 1536–1556. (4) Banszerus, L.; Schmitz, M.; Engels, S.; Dauber, J.; Oellers, M.; Haupt, F.; Watanabe, K.; Taniguchi, T.; Beschoten, B.; Stampfer, C. Ultrahigh-Mobility Graphene Devices from Chemical Vapor Deposition on Reusable Copper. Sci. Adv. 2015, 1, e1500222(1-6). (5) Kim, H. H.; Lee, S. K.; Lee, S. G.; Lee, E.; Cho, K. Wetting-Assisted Crack- and Wrinkle-Free Transfer of Wafer-Scale Graphene onto Arbitrary Substrates over a Wide Range of Surface Energies. Adv. Funct. Mater. 2016,26, 2070-2077. (6) Li, X.; Cai, W.; An, J.; Kim, S.; Nah, J.; Yang, D.; Piner, R.; Velamakanni, A.; Jung, I.; Tutuc, E.; Banerjee,S. K;Colombo, L.; Ruoff. R. S . Large-Area Synthesis of High-Quality and Uniform Graphene Films on Copper Foils. Science . 2009, 324, 1312–1314.