Average Performance Degradation Research Articles

Quantitative Testing and Analysis of Non-Standard AEB Scenarios Extracted from Corner Cases

Existing testing methods for Automatic Emergency Braking (AEB) systems mostly rely on standard-based qualitative analysis of specific scenarios, with a focus on whether collisions occur. To explore scenarios beyond the standard conduct, a comprehensive testing model construction and analysis, and provide a more quantitative evaluation of AEB performance, this study extracted three typical hazardous driving scenarios from the KITTI (The Automated Driving dataset was created by the Karlsruhe Institute of Technology in Germany and the Toyota Institute of Technology in the United States) naturalistic driving dataset using kinematic data. A DME (Data Missing Estimation) scene construction method was proposed, and these scenarios were simulated and reconstructed in PRESCAN (PRESCAN is an automotive simulation software owned by Siemens, Munich, Germany). A C-AEB (Curve-Automatic Emergency Braking) testing model was developed and tested based on simulations. Finally, a BCEM (Boundary collision evaluation model) was proposed to quantitatively evaluate AEB performance. The focus of the analysis was on the identified cornering scenario A (severely failed AEB scenario). A C-AEB testing model was constructed based on the DME scene construction method for this cornering AEB failure scenario, and it was evaluated using the BCEM. The study found that the average performance degradation rate (performance degradation rate refers to the ratio of AEB performance in the current scenario compared to the standard straightaway test) of the AEB system in this cornering scenario reached 75.44%, with a maximum performance degradation rate of 89.47%. It was also discovered that the severe failure of AEB in this cornering scenario was mainly caused by sensor system perception defects and limitations of traditional AEB algorithms. This fully demonstrates the effectiveness of our testing and evaluation methodology.

Numerical study on cavitation reduction using PressurePores technology

The requirements in marine propeller design are rising in quantity and quality in recent decades. Besides hydrodynamic performance demand, the targets in reducing propeller cavitation and its side effects need to be considered such as underwater radiated noise and pressure pulses, to ensure comfort requirements and environmental regulations. Using numerical simulation, the present paper investigates the reduction of propeller tip vortex cavitation (TVC) as well as the effects on its performance by employing PressurePores technology. This study uses the Potsdam Propeller Test Case (PPTC) model with commercial code STAR CCM+. The CFD results are compared with the test results in the cavitation tunnel to validate the reliability of numerical simulation. In addition, cavitation mitigation of the propeller is estimated and an obtained average performance degradation is only 2% for different cases, in terms of pore diameters and drilling methods (cylindrical pore and conus pore). This research also provides the changes in pressure distribution, turbulent viscosity, and vorticity around the propeller to clarify the reason for cavitation reduction together with the hydrodynamic efficiency degradation of the propeller.

인공 신경망 예측기를 이용한 새로운 데이터 모델 기반 PV 어레이 고장 진단용 기준 신호 발생 방법

The power supply part of a PV system is called a PV array which is composed of many PV strings connected in parallel. A PV-string which is a set of PV modules is made by serial connection of many PV modules. PV modules presents irregularity of ouput power which is generated due to various factors such as average performance degradation of about 0.923% to 1.54% according to various researches and born power variations over production stages. Power degradation and born power variation are due to various factors such as material interactions(connection state of connectors between PV cells, corrosion, browning of encapsulation materials ...etc) and environment factors such as shading and soiling which refers to the accumulation of snow, dirt, leaves and bird droppings on PV modules. Such various minor factors can make side effects in safety side and economic one. Therefore several methodology for diagnosis of PV-array have been developed, which are classified into three types – image-based diagnosis approach, model-based approach and data-driven approach. In this paper, a new data-based approach(called data model) with good failure diagnosis reliability and economy is proposed, and verified by simulation using Python, published data and reasonable data generation. Based on the bathtub failure rate function, the fault diagnosis model requires a well-functioning predictor to generate a reference signal which evaluates the output characteristics of PV array under instantaneously varying environmental condition such as solar irradiance, temperature, etc. To implement a new data-based approach, an Artificial Neural Network (ANN) based predictor is applied as a reference generator for PV array’s fault diagnosis. r² value and the RMSE(Root Mean Square Error) are used to evaluate how far away individual learned predictions are from the actual measured values. Based on the reliability obtained from the learning result for a specific PV string, it is confirmed through pair comparison analysis(called t-test) that the learning result(called clustering possibility) between PV strings under different installation conditions is also reliable.

PISCOT: A Pipelined Split-Transaction COTS-Coherent Bus for Multi-Core Real-Time Systems

Tasks in modern embedded systems such as automotive and avionics communicate among each other using shared data towards achieving the desired functionality of the whole system. In commodity platforms, cores communicate data through the shared memory hierarchy and correctness is maintained by a cache coherence protocol. Recent works investigated the deployment of coherence protocols in real-time systems and showed significant performance improvements. Nonetheless, we find these works to require modifications to commodity coherence protocols, assume simple in-order pipelines, and most importantly suffer from significant latency delays due to coherence interference along with average performance degradation. In this work, we propose PISCOT : a predictable and coherent bus architecture that (i) provides a considerably tighter bound compared to the state-of-the-art predictable coherent solutions (4× tighter bounds in a quad-core system). (ii) It does so with a negligible performance loss compared to conventional high-performance architecture coherence delays (less than 4% for SPLASH-3 benchmarks). This improves average performance by up to 5× (2.8× on average) compared to its predictable coherence counterpart. Finally, (iii) it achieves that without requiring any modifications to conventional coherence protocols. We show this by integrating PISCOT on top of two protocols with a detailed implementation with complete transient states: MSI and MESI.

WaFFLe

Managing thermal imbalance in contemporary chip multi-processors (CMPs) is crucial in assuring functional correctness of modern mobile as well as server systems. Localized regions with high activity, e.g., register files, ALUs, FPUs, and so on, experience higher temperatures than the average across the chip and are commonly referred to as hotspots. Hotspots affect functional correctness of the underlying circuitry and a noticeable increase in leakage power, which in turn generates heat in a self-reinforced cycle. Techniques that reduce the severity of or completely eliminate hotspots can maintain functional correctness along with improving performance of CMPs. Conventional dynamic thermal management targets the cores to reduce hotspots but often ignores caches, which are known for their high leakage power consumption. This article presents WaFFLe , an approach that targets the leakage power of the last-level cache (LLC) and hotspots occurring at the cores. WaFFLe turns off LLC-ways to reduce leakage power and to generate on-chip thermal buffers. In addition, fine-grained DVFS is applied during long LLC miss induced stalls to reduce core temperature. Our results show that WaFFLe reduces peak and average temperature of a 16-core based homogeneous tiled CMP with up to 8.4 ֯ C and 6.2 ֯ C, respectively, with an average performance degradation of only 2.5 %. We also show that WaFFLe outperforms a state-of-the-art cache-based technique and a greedy DVFS policy.

Preventing malicious communication using virtualization

Cyber-attacks vary greatly in their goals, methods, and complexity, but they all communicate with their operators. Existing methods that attempt to prevent unauthorized communication are either inadequate or are vulnerable to kernel-mode attacks. We demonstrate the viability of stealthy network transmission on various network interface cards, using only data-writes to physical pages. For some cards, a code-reuse attack is used to issue IO instructions. Finally, the paper describes a virtualization-based method that prevents unauthorized communication. The analysis of its impact on the network bandwidth and the overall system performance shows that the average performance degradation is 0.6% on an idle system and 1.7% with a 10 MB/s outgoing traffic. The bandwidth degrades by 15% on average.

Practically Deploying Heavyweight Adaptive Bitrate Algorithms With Teacher-Student Learning

Major commercial client-side video players employ adaptive bitrate (ABR) algorithms to improve the user quality of experience (QoE). With the evolvement of ABR algorithms, increasingly complex methods such as neural networks have been adopted to pursue better performance. However, these complex methods are too heavyweight to be directly deployed in client devices with limited resources, such as mobile phones. Existing solutions suffer from a trade-off between algorithm performance and deployment overhead. To make the deployment of sophisticated ABR algorithms practical, we propose PiTree, a general, high-performance, and scalable framework that can faithfully convert sophisticated ABR algorithms into decision trees with teacher-student learning. In this way, network operators can train complex models offline and deploy converted lightweight decision trees online. We also present theoretical analysis on the conversion and provide two upper bounds of the prediction error during the conversion and the generalization loss after conversion. Evaluation on three representative ABR algorithms with both trace-driven emulation and real-world experiments demonstrates that PiTree could convert ABR algorithms into decision trees with <; 3% average performance degradation. Moreover, compared to original deployment solutions, PiTree could save considerable operating expenses for content providers.

Propeller tip vortex mitigation by roughness application

In this study, the application of surface roughness on model and full scale marine propellers in order to mitigate tip vortex cavitation is evaluated. To model the turbulence, SST k−ω model along with a curvature correction is employed to simulate the flow on an appropriate grid resolution for tip vortex propagation, at least 32 cells per vortex diameter according to our previous guidelines. The effect of roughness is modelled by modified wall functions. The analysis focuses on two types of vortices appearing on marine propellers: tip vortices developing in lower advance ratio numbers and leading edge tip vortices developing in higher advance ratio numbers. It is shown that as the origin and formation of these two types of vortices differ, different roughness patterns are needed to mitigate them with respect to performance degradation of propeller performance. Our findings clarify that the combination of having roughness on the blade tip and a limited area on the leading edge is the optimum roughness pattern where a reasonable balance between tip vortex cavitation mitigation and performance degradation can be achieved. This pattern in model scale condition leads to an average TVC mitigation of 37% with an average performance degradation of 1.8% while in full scale condition an average TVC mitigation of 22% and performance degradation of 1.4% are obtained.

A Remote Memory Sharing System for Virtualized Computing Infrastructures

Resource management is a critical issue in today’s virtualized computing infrastructures. Consolidation is the main technique used to optimize such infrastructure. Regarding memory management, it allows gathering overloaded and underloaded VM on the same server so that memory can be mutualized. However, because of infrastructures constraints and complexity of managing multiple resources, consolidation can hardly optimize memory management. In this article, we propose to rely on a remote memory sharing for mutualizing memory. We implemented a system which monitors the working set of virtual machines, reclaims unused memory and makes it available (as a remote swap device) for virtual machines which need memory. Our evaluations with HPC and Big Data benchmarks demonstrate the effectiveness of this approach. We show that remote memory can improve the performance of a standard Spark benchmark by up the 17 percent with an average performance degradation of 1.5 percent (for the providing application).

Fine-grained Powercap Allocation for Power-constrained Systems based on Multi-objective Machine Learning

Power capping is an important solution to keep the system within a fixed power constraint. However, for the over-provisioned and power-constrained systems, especially the future exascale supercomputers, powercap needs to be reasonably allocated according to the workloads of compute nodes to achieve trade-offs among performance, energy and powercap. Thus it is necessary to model performance and energy and to predict the optimal powercap allocation strategies. Existing power allocation approaches have insufficient granularity within nodes. Modeling approaches usually model performance and energy separately, ignoring the correlation between objectives, and do not expose the Pareto-optimal powercap configurations. Therefore, this article combines the powercap with uncore frequency scaling and proposes an approach to predict the Pareto-optimal powercap configurations on the power-constrained system for input MPI and OpenMP parallel applications. Our approach first uses the elaborately designed micro-benchmarks and a small number of existing benchmarks to build the training set, and then applies a multi-objective machine learning algorithm which combines the stacked single-target method with extreme gradient boosting to build multi-objective models of performance and energy. The models can be used to predict the optimal processor and memory powercap settings, helping compute nodes perform fine-grained powercap allocation. When the optimal powercap configuration is determined, the uncore frequency scaling is used to further optimize the energy consumption. Compared with the reference powercap configuration, the predicted optimal configurations predicted by our method can achieve an average powercap reduction of 31.35 percent, an average energy reduction of 12.32 percent, and average performance degradation of only 2.43 percent.

Hardware-Assisted MMU Redirection for In-Guest Monitoring and API Profiling

With the advance of hardware, network, and virtualization technologies, cloud computing has prevailed and become the target of security threats such as the cross virtual machine (VM) side channel attack, with which malicious users exploit vulnerabilities to gain information or access to other guest virtual machines. Among the many virtualization technologies, the hypervisor manages the shared resource pool to ensure that the guest VMs can be properly served and isolated from each other. However, while managing the shared hardware resources, due to the presence of the virtualization layer and different CPU modes (root and non-root mode), when a CPU is switched to non-root mode and is occupied by a guest machine, a hypervisor cannot intervene with a guest at runtime. Thus, the execution status of a guest is like a black box to a hypervisor, and the hypervisor cannot mediate possible malicious behavior at runtime. To rectify this, we propose a hardware-assisted VMI (virtual machine introspection) based in-guest process monitoring mechanism which supports monitoring and management applications such as process profiling. The mechanism allows hooks placed within a target process (which the security expert selects to monitor and profile) of a guest virtual machine and handles hook invocations via the hypervisor. In order to facilitate the needed monitoring and/or management operations in the guest machine, the mechanism redirects access to in-guest memory space to a controlled, self-defined memory within the hypervisor by modifying the extended page table (EPT) to minimize guest and host machine switches. The advantages of the proposed mechanism include transparency, high performance, and comprehensive semantics. To demonstrate the capability of the proposed mechanism, we develop an API profiling system (APIf) to record the API invocations of the target process. The experimental results show an average performance degradation of about 2.32%, far better than existing similar systems.

Traffic Sign Detection Under Challenging Conditions: A Deeper Look into Performance Variations and Spectral Characteristics

Traffic signs are critical for maintaining the safety and efficiency of our roads. Therefore, we need to carefully assess the capabilities and limitations of automated traffic sign detection systems. Existing traffic sign datasets are limited in terms of type and severity of challenging conditions. Metadata corresponding to these conditions are unavailable and it is not possible to investigate the effect of a single factor because of simultaneous changes in numerous conditions. To overcome the shortcomings in existing datasets, we introduced the CURE-TSD-Real dataset, which is based on simulated challenging conditions that correspond to adversaries that can occur in real-world environments and systems. We test the performance of two benchmark algorithms and show that severe conditions can result in an average performance degradation of 29% in precision and 68% in recall. We investigate the effect of challenging conditions through spectral analysis and show that challenging conditions can lead to distinct magnitude spectrum characteristics. Moreover, we show that mean magnitude spectrum of changes in video sequences under challenging conditions can be an indicator of detection performance. CURE-TSD-Real dataset is available online at https://github.com/olivesgatech/CURE-TSD.

Isolating Speculative Data to Prevent Transient Execution Attacks

Hardware security has recently re-surfaced as a first-order concern to the confidentiality protections of computing systems. Meltdown and Spectre introduced a new class of exploits that leverage transient state as an attack surface and have revealed fundamental security vulnerabilities of speculative execution in high-performance processors. These attacks derive benefit from the fact that programs may speculatively execute instructions outside their legal control flows. This insight is then utilized for gaining access to restricted data and exfiltrating it by means of a covert channel. This study presents a microarchitectural mitigation technique for shielding transient state from covert channels during speculative execution. Unlike prior work that has focused on closing individual covert channels used to leak sensitive information, this approach prevents the use of speculative data by downstream instructions until doing so is determined to be safe. This prevents transient execution attacks at a cost of 18 percent average performance degradation.

Experimental validation of performance and degradation study of canal-top photovoltaic system

The canal-top PV systems have different environmental conditions than the land-based system which may affect its performance and degradation rate. The performance and reliability of PV modules on the canal and reservoir are critical for ensuring the long lifetime, improvement and economic viability of the canal-top PV systems. The long-term performance analysis of the canal-top PV systems and their comparison with conventional land-based PV systems is not reported widely. The objective of the present study is to assess the suitability of PV systems on the canals for their large scale installations and reliable operation. In order to understand the long-term performance behavior of the PV systems on the canals, the performance and degradation analysis of world’s first commercial multicrystallinesilicon (Multi-Si) based 10 MWp canal-top PV system installed in the Indian state of Gujarat has been carried out for their initial 2 years 8 months operation. An experimental setup was fabricated to compare the performance of canal-top PV systems with the conventional land-based PV systems and measurements were carried out in the outdoor conditions for six months in the outdoor laboratory of Indian Institute of Technology Roorkee, India. To achieve a better understanding of the performance and degradation of PV modules, a single-diode PV model was developed to characterize the PV modules. Furthermore, the evaporation loss reduction by canal-top PV systems has not been reported widely and has been experimentally quantified under this study. The annual average performance ratio and degradation rate of 10 MWp canal-top PV system are found to be 77.85% and 1.93 ± 0.28%/year, respectively. Experimental comparison of water tank-based PV module and land-based PV module shows that the average performance ratio of Multi-Si module on the water surface is about 1.5% lower compared to land-based Multi-Si module which is contrary to the general perception of higher power production by the Multi-Si PV systems on the canals.

Performance analysis of field-exposed multicrystalline silicon photovoltaic modules over 30 years

In this paper, we present the energy performance and degradation of multicrystalline silicon photovoltaic (PV) modules after a 30-year operation under hot and humid climatic conditions. A comprehensive analysis was conducted by visual inspection, electrical performance evaluation, and system final yield evaluation. Visual inspection revealed the yellowing and delamination of ethylene vinyl acetate (EVA), and cracks in the backsheet were found to be the most frequent defects. It is possible to perform a comparison between final and initial parameters. The average performance degradation over 30 years from 1986 to 2016 is 6.51%. The annual average degradation has been found to be only 0.22%/year. System output power and performance ratio (PR) were also analyzed, giving an annual PR of 69.72%. These results indicate that the actual lifetime of PV modules is significantly longer than the warranty periods of 25 years, and still with good performance and reliability.

Filtering Translation Bandwidth with Virtual Caching

Heterogeneous computing with GPUs integrated on the same chip as CPUs is ubiquitous, and to increase programmability many of these systems support virtual address accesses from GPU hardware. However, this entails address translation on every memory access. We observe that future GPUs and workloads show very high bandwidth demands (up to 4 accesses per cycle in some cases) for shared address translation hardware due to frequent private TLB misses. This greatly impacts performance (32% average performance degradation relative to an ideal MMU). To mitigate this overhead, we propose a software-agnostic, practical, GPU virtual cache hierarchy. We use the virtual cache hierarchy as an effective address translation bandwidth filter. We observe many requests that miss in private TLBs find corresponding valid data in the GPU cache hierarchy. With a GPU virtual cache hierarchy, these TLB misses can be filtered (i.e., virtual cache hits), significantly reducing bandwidth demands for the shared address translation hardware. In addition, accelerator-specific attributes (e.g., less likelihood of synonyms) of GPUs reduce the design complexity of virtual caches, making a whole virtual cache hierarchy (including a shared L2 cache) practical for GPUs. Our evaluation shows that the entire GPU virtual cache hierarchy effectively filters the high address translation bandwidth, achieving almost the same performance as an ideal MMU. We also evaluate L1-only virtual cache designs and show that using a whole virtual cache hierarchy obtains additional performance benefits (1.31× speedup on average).

Performance of Mode Space Detector in Uncertain Shallow Water and Its Robust Realization

The statistics of the mode space detector (MSD) whose modes are characterized by some degree of mismatch to truth [that is, the mismatched mode space detector (MMSD)] are derived. As a measure of the “containing relation” between the mode spaces derived from different environmental realizations we propose the relative projection error metric, through which the performance of the MMSD can be further investigated and compared to the MSD using accurate environmental knowledge. From this performance analysis, we suggest that by simply using the greatest dimensional physically supported mode space, we can obtain a robust MSD. It can achieve the same performance robustness as the energy detector—the performance is only determined by the array signal energy and is insensitive to the specific source position and environmental conditions. It can also avoid the potentially-significant performance degradation of the Bayesian detector when applied to certain deterministic scenarios at a cost of small average performance degradation. Numerical simulations in a typical uncertain shallow-water environment support our assertions.

Secure Hierarchy-Aware Cache Replacement Policy (SHARP)

In cache-based side channel attacks, a spy that shares a cache with a victim probes cache locations to extract information on the victim's access patterns. For example, in evict+reload, the spy repeatedly evicts and then reloads a probe address, checking if the victim has accessed the address in between the two operations. While there are many proposals to combat these cache attacks, they all have limitations: they either hurt performance, require programmer intervention, or can only defend against some types of attacks. This paper makes the following observation for an environment with an inclusive cache hierarchy: when the spy evicts the probe address from the shared cache, the address will also be evicted from the private cache of the victim process, creating an inclusion victim. Consequently, to disable cache attacks, this paper proposes to alter the line replacement algorithm of the shared cache, to prevent a process from creating inclusion victims in the caches of cores running other processes. By enforcing this rule, the spy cannot evict the probe address from the shared cache and, hence, cannot glimpse any information on the victim's access patterns. We call our proposal SHARP (Secure Hierarchy-Aware cache Replacement Policy). SHARP efficiently defends against all existing cross-core shared-cache attacks, needs only minimal hardware modifications, and requires no code modifications. We implement SHARP in a cycle-level full-system simulator. We show that it protects against real-world attacks, and that it introduces negligible average performance degradation.

An adaptive cache coherence protocol: Trading storage for traffic

This paper introduces a new adaptive cache coherence protocol which minimizes energy requirements and guarantees scalability. It includes two complementary parts: a non-inclusive sparse-directory to track only actively shared blocks and a structure to determine the presence of a block in the private caches based on an improved counting bloom filter. It uses token counting to preserve the system correctness, to improve performance and to reduce the implementation complexity. Combining all these characteristics, the proposal has a low storage overhead and is able to suppress most of the traffic inherent to snoop-based protocols and reduce the size of directory-based structures. Using a capacity to track only 40% of all the blocks allocated in the private caches, this coherence protocol is able to achieve better performance than an over-provisioned sparse-directory with a capacity to track 160% of the blocks kept in private caches. The complementarity of both structures enables the coherence controller to change dynamically the way the storage available is dedicated according to the data-sharing properties of the application. Thus, applications with high-sharing degree will need more directory space while low-sharing degree patterns will need more private block-presence space to include more information. With only 5% of the private cache entries tracked, the average performance degradation is less than 8% compared to a 160% over-provisioned sparse-directory.

Dirigent

Latency-critical applications suffer from both average performance degradation and reduced completion time predictability when collocated with batch tasks. Such variation forces the system to overprovision resources to ensure Quality of Service (QoS) for latency-critical tasks, degrading overall system throughput. We explore the causes of this variation and exploit the opportunities of mitigating variation directly to simultaneously improve both QoS and utilization. We develop, implement, and evaluate Dirigent, a lightweight performance-management runtime system that accurately controls the QoS of latency-critical applications at fine time scales, leveraging existing architecture mechanisms. We evaluate Dirigent on a real machine and show that it is significantly more effective than configurations representative of prior schemes.