Average Performance Degradation Research Articles

Dirigent

Latency-critical applications suffer from both average performance degradation and reduced completion time predictability when collocated with batch tasks. Such variation forces the system to overprovision resources to ensure Quality of Service (QoS) for latency-critical tasks, degrading overall system throughput. We explore the causes of this variation and exploit the opportunities of mitigating variation directly to simultaneously improve both QoS and utilization. We develop, implement, and evaluate Dirigent, a lightweight performance-management runtime system that accurately controls the QoS of latency-critical applications at fine time scales, leveraging existing architecture mechanisms. We evaluate Dirigent on a real machine and show that it is significantly more effective than configurations representative of prior schemes.

A CLOSED LOOP POWER MANAGER FOR TRANSMISSION POWER CONTROL IN WIRELESS NETWORK-ON-CHIP ARCHITECTURES

In wireless Network-on-Chip (WiNoC), radio frequency (RF) transceivers account for a significant power consumption, particularly its transmitter, out of its total communication energy. Current WiNoC architectures employ constant maximum transmitting power for communicating radio hubs regardless of physical location of the receiver radio hubs. This paper proposes a closed loop transmitting power control mechanism that, using bit error rate (BER) report obtained at receiver’s side, dynamically calibrates the transmitting power level needed for communication between the source and destination radio hubs to guarantee transmission reliability. Our proposed strategy achieves a significant total system energy reduction by about 40% with an average performance degradation of 3%.

An Adaptive Thread Scheduling Mechanism With Low-Power Register File for Mobile GPUs

In response to the remarkable increase in 3D applications in consumer electronics devices in recent years, graphics processing units (GPUs) have become widely available on mobile devices. These GPUs typically use hardware multithreaded shaders to improve their throughputs for real-time rendering, but they depend on duplicate register files to maintain the context of each hardware thread, increasing power consumption. However, the register usage of shading programs is often relatively low, which causes many registers to remain unused, thus wasting power. Long latency memory operations can also consume unnecessary power to activate registers. This study proposes a low-power register file with multiple power modes to reduce the power consumption of the register file. This study also presents an adaptive thread scheduling mechanism to achieve a tradeoff between the power consumption of the register file and frames per second (FPS). Results show that the average performance degradation from the proposed low-power register file is only 0.62%. The proposed adaptive thread scheduling has average under prediction ratio of 3.32%. The leakage reduction of the proposed low-power register file is 74.80%. This reduction can be improved to 81.49%, 82.22%, and 84.28% with adaptive thread scheduling at frame rates of 30, 25, and 20, respectively.

Virtual machine consolidation based on interference modeling

Server consolidation is very attractive for cloud computing platforms to improve energy efficiency and resource utilization. Advances in multi-core processors and virtualization technologies have enabled many workloads to be consolidated in a physical server. However, current virtualization technologies do not ensure performance isolation among guest virtual machines, which results in degraded performance due to contention in shared resources along with violation of service level agreement (SLA) of the cloud service. In that sense, minimizing performance interference among co-located virtual machines is the key factor of successful server consolidation policy in the cloud computing platforms. In this work, we propose a performance model that considers interferences in the shared last-level cache and memory bus. Our performance interference model can estimate how much an application will hurt others and how much an application will suffer from others. We also present a virtual machine consolidation method called swim which is based on our interference model. Experimental results show that the average performance degradation ratio by swim is comparable to the optimal allocation.

Bounds and parameter optimization of medium access control coding for wireless ad hoc and sensor networks

The use of codes to schedule transmissions is an attractive technique able to guarantee a non-zero throughput medium access performance for the nodes of a wireless ad hoc or sensor network regardless of network topology variations. Some authors refer to this technique as topology-transparent scheduling. In this paper, we use the term MAC coding in order to emphasize the exclusive use of codes to achieve topology-transparency within the MAC sub-layer. We present a new upper bound expression on the guaranteed throughput achievable by any linear code used in a MAC coding context. This bound proves to be tighter than the one obtained when the minimum distance of the code is equal to its length. Additionally, we derive new and simple closed analytical expressions for the parameters of maximum distance separable codes that maximize the minimum, average, or joint minimum–average throughput of MAC coding. The optimization methods presented here are also applicable to other codes with available analytical expressions for their minimum distance and distance distribution. Finally, we present system-level simulation results of MAC coding on static and dynamic topologies with mobility and including wireless channel errors. Throughput simulation results are compared with their corresponding analytical expressions and to a random scheduling approach. The results show agreement with analysis and confirm the robustness of MAC coding in maintaining minimum levels of performance with good average performance and graceful degradation.

Exploiting program phase behavior for energy reduction on multi-configuration processors

Energy consumption is a major design issue for modern microprocessors. In previous work, several techniques were presented to reduce the overall energy consumption by dynamically adapting various hardware structures. Most approaches however lack the ability to deal efficiently with the configuration space explosion in case of multiple adaptive structures. In this paper, we present a mechanism that is able to deal with this configuration space problem. We first identify phases through profiling using a new phase classification method and determine the optimal hardware configuration per phase using an efficient offline search algorithm. During program execution, we inspect the phase behavior and adapt the hardware on a per-phase basis. Using SPEC2000 benchmarks, we show that the proposed mechanism achieves an energy reduction of 36% on average with an average performance degradation of only 2.9%. We also show that online processor configuration optimization is far less effective for multi-configuration processors, with an average energy reduction of less than 20% for comparable performance degradations.

SmashGuard: A Hardware Solution to Prevent Security Attacks on the Function Return Address

A buffer overflow attack is perhaps the most common attack used to compromise the security of a host. This attack can be used to change the function return address and redirect execution to the attacker's code. We present a hardware-based solution, called SmashGuard, to protect against all known forms of attack on the function return addresses stored on the program stack. With each function call instruction, the current return address is pushed onto a hardware stack. A return instruction compares its address to the return address from the top of the hardware stack. An exception is raised to signal the mismatch. Because the stack operations and checks are done in hardware in parallel with the usual execution of instructions, our best-performing implementation scheme has virtually no performance overhead (because we are modifying hardware, it is impossible to guarantee zero overhead without an actual hardware implementation). While previous software-based approaches' average performance degradation for the SPEC2000 benchmarks is only 2.8 percent, their worst-case degradation is up to 8.3 percent. Apart from the lack of robustness in performance, the software approaches' key disadvantages are less security coverage and the need for recompilation of applications. SmashGuard, on the other hand, is secure and does not require recompilation of applications.

Optimal prefiltering in iterative feedback tuning

Iterative feedback tuning (IFT) is a data-based method for the iterative tuning of restricted complexity controllers. A special experiment in which a batch of previously collected output data is fed back at the reference input allows one to compute an unbiased estimate of the gradient of the control performance criterion. We show that, by performing an optimal filtering of the data that are fed back, one can minimize the asymptotic variability of the control performance cost and, hence, minimize the average performance degradation that results from the randomness of the data. The expression of the optimal filter is derived, and a simulation illustrates the benefits that result from using this optimal filter as compared to the use of the classical constant filter.

Pipeline damping

Scaling of CMOS technology causes the power supply voltages to fall and supply currents to rise at the same time as operating speeds are increasing. Falling supply voltages cause noise margins to decrease, while increasing current and frequency makes supply noise injection larger, especially noise caused by inductance in the supply lines. Creating power distribution systems is one of the key challenges in modern chip design. Decoupling capacitance helps reduce inductance effects, but there is often a peak in the supply impedance that occurs at a resonant frequency caused roughly by the package inductance and the chip decoupling capacitors. This frequency is on the order of 100MHz, which is much lower than the operating frequency of the processor. We propose pipeline damping, an architectural technique which controls instruction issue to guarantee bounds on current variation around the frequency of the supply resonance, thus reducing the resulting supply noise. Damping is a cheaper alternative to expensive, circuit-based noise-reduction techniques. We make the fundamental observation that limiting the current flow change (di) within resonant time period (dt) controls di/dt without large performance loss. Damping guarantees bounds on current variation while allowing processor current to increase or decrease to the magnitude required to maintain performance. Our results show that a damped processor guarantees a 33% reduction in the worst-case current variation with an average performance degradation of 7% and average energy delay of 1.09 compared to an undamped processor.

Reconfigurable Tree Architectures for Gracefully Degradable VLSI Systems

Several families of reconfigurable tree-like architectures, suitable for VLSI implementation, are presented. Such architectures are based on interconnection patterns consisting of complete binary trees with spare links added (between a node and its grandfather and/or cousin) according to various criteria. The aim is to dynamically reconfigure them as (nonbinary) trees. The total silicon area required by these architectures is only a constant factor higher than that of a complete binary tree. They can bear multiple faults in processing elements and/or links and still function with an acceptable performance degradation. An analytical method for evaluating the average performance degradation in the presence of faults is presented. Some basic procedure paradigms that can be easily performed on all the proposed architectures are given. Such paradigms can be effectively used in several applications, including linear programming, dictionary machines, and relational database processing.

Efficient search and design procedures for robust multi-stage VQ of LPC parameters for 4 kb/s speech coding

A tree-searched multistage vector quantization (VQ) scheme for linear prediction coding (LPC) parameters which achieves spectral distortion lower than 1 dB with low complexity and good robustness using rates as low as 22 b/frame is presented. The M-L search is used, and it is shown that it achieves performance close to that of the optimal search for a relatively small M. A joint codebook design strategy for multistage VQ which improves convergence speed and the VQ performance measures is presented. The best performance/complexity tradeoffs are obtained with relatively small size codebooks cascaded in a 3-6 stage configuration. It is shown experimentally that as the number of stages is increased above the optimal performance/complexity tradeoff, the quantizer robustness and outlier performance can be improved at the expense of a slight increase in rate. Results for log area ratio (LAR) and line spectral pairs (LSPs) parameters are presented. A training technique that reduces outliers at the expense of a slight average performance degradation is introduced. The method significantly outperforms the split codebook approach.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>