Avalanche Energy Research Articles

Tuning Avalanche Path in Vertical GaN JFETs By Gate Driver Design

The 1.2-kV vertical gallium nitride (GaN) fin-channel junction-gate field-effect transistor (JFET) has recently emerged as a promising candidate for power electronics. It is normally <small>off</small> and has a specific <small>on</small>-resistance smaller than that of 1.2-kV SiC <small>mosfets</small>. A robust avalanche capability has also been reported in vertical GaN JFETs with an avalanche current flowing through the gate. This avalanche path differs from that of power <small>mosfets</small> (via the source) and may pose challenges in gate driver reliability. This article, for the first time, demonstrates that the avalanche current in GaN JFETs can be tuned to flow through the source, by using either a <small>mosfet</small> driver with a large gate resistance or an <i>RC</i>-interface driver. These drivers turn <small>on</small> the fin channel during the device avalanche and obviate a large avalanche current into the gate driver. The carrier dynamics within the GaN JFET under the two avalanche paths have been unveiled by physics-based mixed-mode electrothermal simulations. The critical avalanche energy density in both paths was found to be comparable with the state-of-the-art SiC <small>mosfet</small>s. Additionally, the <i>RC</i>-interface driver was shown to outperform the <small>mosfet</small> driver for vertical GaN JFETs. The learning about normally <small>off</small> GaN JFETs was applied to a study of commercial normally <small>on</small> SiC JFETs. Two avalanche paths of a similar nature were observed with different gate drivers. This article provides new insights of the JFET avalanche and show the excellent robustness of the novel 1.2 kV vertical GaN JFET.

Experiment and analysis of repetitive avalanche low-current stress on 4H-SiC power devices

As a kind of 4H-SiC power device, the junction barrier Schottky (JBS) rectifiers, only containing the transition p + implantation region at the edge of the active region in the termination region, are adopted and fabricated to analyze the effect of the repetitive avalanche low-current stress on the SiO2/4H-SiC interfacial state of the devices. The breakdown voltage (BV) of the device shifts after the repetitive avalanche current stress, which results from the electron injects into the SiO2/4H-SiC interface and trapped by the interface states. Meanwhile, there is a tradeoff between the quantities of the trapped and de-trapped electrons by the SiO2/4H-SiC interface states when the BV reaches its saturated value. The junction temperature, total amount of carriers generated in the single avalanche event and repetitive total avalanche energy, affected by the pulse period (T), pulse number and turn-on period (D), are the key factors that affect the level of the BV shift.

Robust Through-Fin Avalanche in Vertical GaN Fin-JFET With Soft Failure Mode

We study the inherent ruggedness of the avalanche through the fin channel, a new avalanche mode in a vertical GaN power Fin-JFET, through single-pulse and repetitive avalanche circuit tests. By turning on the gate during avalanche, the major avalanche current path migrates from the p-GaN gate to the n-GaN fin channel. The single-pulse critical avalanche energy density ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {AVA}}$ </tex-math></inline-formula> ) was measured to be 10 J/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , which is the highest reported in GaN transistors. The Fin-JFET withstood over 3700 repetitive avalanche pulses at 70% of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {AVA}}$ </tex-math></inline-formula> . It exhibits a failure-to-open-circuit signature in single and repetitive avalanche. This soft failure mode allows the device to retain its full breakdown voltage, which is highly desirable for system robustness. By contrast, the through-gate avalanche in Fin-JFETs and the reported avalanche in Si and SiC transistors all show a destructive, failure-to-short-circuit signature. These results show the viability of soft avalanche failure in power devices, provide key robustness references for GaN devices, and suggest the fundamental superiority of moving the avalanche path away from the major blocking junction.

Analytical Expressions of Time-Domain Responses of Protection Circuits to ISO Reverse Transients in Automotive Applications

As the use of semiconductors and electronic control units (ECU) in automobiles has increased, electromagnetic susceptibility has become more essential for the reliability of ECUs. Consequently, automotive ECUs are subjected to electromagnetic compatibility tests to control quality. Test pulses for electromagnetic immunity testing in the automotive industry, such as reverse transients 1 and 3a, defined in the International Organization for Standardization (ISO) 7637&#x2013;2 standard document, are examined. In practice, it is necessary to analytically investigate the performance of the protection circuits against these reverse pulses. In this paper, theoretical expressions of the time-domain responses of the capacitor filter to these reverse pulses are derived. In addition, the expressions of the avalanche energy as well as the time during avalanche mode are presented. The analytical results, validated by LTspice simulation, show that for the case of pulse 1, the reversal battery-polarity protection device after the filter, i.e., a low-voltage power metal-oxide-semiconductor field-effect transistor (MOSFET), is safe despite entering the avalanche breakdown mode. In the case of pulse 3a, the filter can almost completely remove the transient voltage and hence avoid the avalanche effect of the MOSFET. The verified expressions when the suppressed voltage reaches its maximum are very helpful for hardware design engineers to quickly determine whether the MOSFET undergoes avalanche breakdown.

SiC double-trench MOSFETs with source-recessed structure for enhanced ruggedness

A novel SiC double-trench MOSFET (DT-MOS) with source-recessed structure is proposed and investigated via Sentaurus TCAD simulations in this paper. The lateral resistance area beneath the source region is completely eliminated, thus suppressing the turn-on of the parasitic npn transistor effectively. As a result, the short-circuit withstanding time, the single pulse avalanche energy (E av) under unclamped inductive switching test and the threshold voltage for single-event burnout are improved by 28%, 14% and 67%, respectively, when compared to the traditional state-of-the-art SiC DT-MOS, indicating its great potential for harsh environment applications.

Surge Current and Avalanche Ruggedness of 1.2-kV Vertical GaN p-n Diodes

This letter reports the avalanche and surge current ruggedness of the industry's first 1.2-kV-class vertical GaN p-n diodes fabricated on 100-mm GaN substrates. The 1.2-kV vertical GaN p-n diodes with a 1.39-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> device area and an avalanche breakdown voltage of 1589 V show a critical avalanche energy density of 7.6 J/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in unclamped inductive switching tests, as well as a critical surge current of 54 A and a critical surge energy density of 180 J/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in 10-ms surge current tests. All these values are the highest reported in vertical GaN devices and comparable to those of commercial SiC p-n diodes and merged p-n Schottky diodes. These GaN p-n diodes show significantly smaller reverse recovery compared to SiC p-n diodes, revealing less conductivity modulation in n-GaN. The negative temperature coefficient of differential on-resistance and the anticlockwise surge <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I–V</i> locus are believed to be due to the increased acceptor ionization in p-GaN and the decreased contact resistance at high temperatures. These results suggest a high ruggedness of GaN p-n junctions with small bipolar currents and fast switching capabilities. As the first electrothermal ruggedness data for industry's vertical GaN devices, these results provide key new insights for the development of vertical GaN devices as well as their application spaces.

Demonstration of Avalanche and Surge Current Robustness in GaN Junction Barrier Schottky Diode With 600-V/10-A Switching Capability

In this letter, we achieved significantly enhanced avalanche ruggedness and surge current capability in GaN junction barrier Schottky (JBS) diode for highly reliable power operation. Based on the selective Mg-ion implantation technology, the GaN JBS diode obtains superior electrostatic performances, including 830-V breakdown voltage, 150-mΩ specific on-state resistance, and 0.5-V turning on voltage. Meanwhile, zero reverse recovery behaviors are observed even under extreme switching conditions of 600 V/10 A. During the reliability evaluation in the inductive load circuits, crucial avalanche capability with avalanche breakdown voltage over 965 V, avalanche energy up to 57.8 mJ, and more than 10 000 repetitive avalanche breakdown events are demonstrated. Together with the surge current tolerance up to 65 A and surge energy of 6.0 J, a large safe-operation-area under both forward and reverse inductive spikes is realized for the GaN-based rectifier.

The duration-energy-size enigma for acoustic emission

Acoustic emission (AE) measurements of avalanches in different systems, such as domain movements in ferroics or the collapse of voids in porous materials, cannot be compared with model predictions without a detailed analysis of the AE process. In particular, most AE experiments scale the avalanche energy E, maximum amplitude Amax and duration D as E ~ Amaxx and Amax ~ Dχ with x = 2 and a poorly defined power law distribution for the duration. In contrast, simple mean field theory (MFT) predicts that x = 3 and χ = 2. The disagreement is due to details of the AE measurements: the initial acoustic strain signal of an avalanche is modified by the propagation of the acoustic wave, which is then measured by the detector. We demonstrate, by simple model simulations, that typical avalanches follow the observed AE results with x = 2 and ‘half-moon’ shapes for the cross-correlation. Furthermore, the size S of an avalanche does not always scale as the square of the maximum AE avalanche amplitude Amax as predicted by MFT but scales linearly S ~ Amax. We propose that the AE rise time reflects the atomistic avalanche time profile better than the duration of the AE signal.

1.2-kV Vertical GaN Fin-JFETs: High-Temperature Characteristics and Avalanche Capability

This work describes the high-temperature performance and avalanche capability of normally- off 1.2-K V-CLASS vertical gallium nitride (GaN) fin-channel junction field-effect transistors (Fin-JFETs). The GaN Fin-JFETs were fabricated by NexGen Power Systems, Inc. on 100-mm GaN-on-GaN wafers. The threshold voltage ( ${V}_{\text {TH}}$ ) is over 2 V with less than 0.15 V shift from 25 °C to 200 °C. The specific ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ) increases from 0.82 at 25 °C to 1.8 $\text{m}\Omega \cdot $ cm2 at 200 °C. The thermal stability of ${V}_{\text {TH}}$ and ${R}_{ \mathrm{\scriptscriptstyle ON}}$ are superior to the values reported in SiC MOSFETs and JFETs. At 200 °C, the gate leakage and drain leakage currents remain below $100~\mu \text{A}$ at −7-V gate bias and 1200-V drain bias, respectively. The gate leakage current mechanism is consistent with carrier hopping across the lateral p-n junction. The high-bias drain leakage current can be well described by the Poole–Frenkel (PF) emission model. An avalanche breakdown voltage ( $BV_{\!\!\text {AVA}}$ ) with positive temperature coefficient is shown in both the quasi-static ${I}$ – ${V}$ sweep and the unclamped inductive switching (UIS) tests. The UIS tests also reveal a $BV_{\!\!\text {AVA}}$ over 1700 V and a critical avalanche energy ( ${E}_{\text {AVA}}$ ) of 7.44 J/cm2, with the ${E}_{\text {AVA}}$ comparable to that of state-of-the-art SiC MOSFETs. These results show the great potentials of vertical GaN Fin-JFETs for medium-voltage power electronics applications.

Avalanche Breakdown in 4H-SiC Schottky Diodes: Reliability Aspects

We consider problems associated with the reliability of high-power 4H-SiC Schottky diodes (SDs) during short-term electric overloads in the reverse direction (for diodes operating in the pulsed avalanche regime). In particular, we analyze the effect of nonuniformity of an avalanche breakdown over the diode area on the maximal avalanche energy (MAE) that can be dissipated by the diode prior to its secondary thermal breakdown. For estimating the uniformity of an avalanche breakdown, we propose that the measured pulse reverse current–voltage (I–V) characteristic of the diode be compared with the calculated I–V characteristic of an ideal quasi-one-dimensional diode. We measured reverse I–V characteristics of commercial 4H-SiC SDs: single avalanche current pulses with a duration of ~1 μs were passed through the diodes; during measurements, the pulse amplitudes grew to values for which a catastrophic failure of diodes occurred. It is shown that an increase in the differential resistance of diodes on the avalanche segment of the I–V curve and a decrease in the extrapolated breakdown voltage (as compared to values calculated for ideal diodes) can lead to a decrease in the MAE.

Comprehensive Assessment of Avalanche Operating Boundary of SiC Planar/Trench MOSFET in Cryogenic Applications

The avalanche ruggedness of power devices becomes a crucial issue to ensure the safe operation of the power conversion systems, particularly under the extreme temperature conditions. In this article, the avalanche capability of SiC planar/trench MOSFETs is systematically evaluated and analyzed over the temperature range of 90 to 340 K. Importantly, the essential mechanisms and temperature dependence of avalanche failure under cryogenic conditions are further explored by combining many analysis methods such as TCAD simulations, the unclamped inductive switching characterizations, and the transient junction temperature prediction. The highest avalanche energy density of 171.24 mJ/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at 90K indicates the great application potential of SiC plannar mosfet in cryogenic electronics. Moreover, the safe avalanche operation boundary (AOB) model is established over the cryogenic temperature range. The relevant analysis method and AOB model can be used to accurately evaluate and quantitatively predict the avalanche capability of SiC planar/trench mosfets for the cryogenic converter design.

Trap-Mediated Avalanche in Large-Area 1.2 kV Vertical GaN p-n Diodes

This work studies the avalanche characteristics of the 1.2 kV vertical GaN p-n diodes with implanted edge termination, based on quasi-static current-voltage ( I-V ) sweeps and unclamped inductive switching (UIS) tests. The UIS tests reveal a ~1.7 kV avalanche breakdown voltage ( $BV_{{\text {AVA}}}{)}$ , 51 A maximum avalanche current ( ${I}_{{\text {AVA}}}{)}$ , and 63 mJ maximum avalanche energy ( ${E}_{{\text {AVA}}}$ ). The ${I}_{{\text {AVA}}}$ and ${E}_{{\text {AVA}}}$ are the highest reported in high-voltage GaN power devices. A lower $BV_{{\text {AVA}}}$ is observed in the I-V curves and a trap mediated avalanche model is proposed to explain it. The $BV_{{\text {AVA}}}$ in I-V curves is believed to be induced by avalanche-assisted trap-filling in the edge termination region, while the $BV_{{\text {AVA}}}$ in the UIS test reflects the robust avalanche at the main p-n junction. These results provide important new insights on the avalanche breakdown in GaN devices and address some seemingly contrary observations of vertical GaN p-n diodes published recently.

Non-trivial avalanches triggered by shear banding in compression of metallic glass foams

Ductile metallic glass foams (DMGFs) are a new type of structural material with a perfect combination of high strength and toughness. Owing to their disordered atomic-scale microstructures and randomly distributed macroscopic voids, the compressive deformation of DMGFs proceeds through multiple nanoscale shear bands accompanied by local fracture of cellular structures, which induces avalanche-like intermittences in stress–strain curves. In this paper, we present a statistical analysis, including distributions of avalanche size, energy dissipation, waiting times and aftershock sequence, on such a complex dynamic process, which is dominated by shear banding. After eliminating the influence of structural disorder, we demonstrate that, in contrast to the mean-field results of their brittle counterparts, scaling laws in DMGFs are characterized by different exponents. It is shown that the occurrence of non-trivial scaling behaviours is attributed to the localized plastic yielding, which effectively prevents the system from building up a long-range correlation. This accounts for the high structural stability and energy absorption performance of DMGFs. Furthermore, our results suggest that such shear banding dynamics introduce an additional characteristic time scale, which leads to a universal gamma distribution of waiting times.

Avalanche Ruggedness Assessment of 1.2kV 45mΩ Asymmetric Trench SiC MOSFETs

In this paper, avalanche ruggedness of the commercial 1.2kV 45mΩ asymmetric silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) is investigated by single-pulse unclamped inductive switching (UIS) test. The avalanche safe operation area (SOA) of the MOSFET is established. The impact of inductance and temperature on avalanche capability is exhibited, which is valuable for many application circuits. The variation in critical avalanche energy with peak avalanche current, peak avalanche current with avalanche time, and temperatures dependence of critical avalanche energy are confirmed.

1200 V / 200 A V-Groove Trench MOSFET Optimized for Low Power Loss and High Reliability

1200 V / 200 A V-groove trench MOSFET optimized to achieve low power loss, high oxide reliability under a drain bias condition and high avalanche ruggedness is shown in this paper. We revealed a relationship between the lifetime under a high temperature reverse bias condition and the oxide electric field. In accordance with the results of the test, the 1200 V / 200 A trench MOSFET showed an improvement in the tradeoff between the on-resistance and oxide electric field with the presence of current spreading layers. In order to obtain low on-resistance and high avalanche ruggedness at the same time, buried guard ring structures, which made the blocking voltage of the edge termination area higher than that of the active area, was developed. The fabricated MOSFETs demonstrated a low specific on-resistance of 3.1 mΩ cm2. A predicted lifetime of 200 years under a high temperature drain bias condition of 1200 V was achieved by the optimized design. A short circuit withstand time of 6 μs and a high avalanche energy of 7.8 J/cm2 were shown.

Influence of transition metal ions: Broad band upconversion emission in thermally stable phosphors

Abstract Frequency upconversion (UC) study at different temperatures in Ho3+/Yb3+/Mn4+:SnO2 phosphors, prepared via solid state reaction method has been performed. The prepared phosphors have been characterized via XRD, Raman spectra, FESEM, EDAX, XPS and diffuse reflectance analysis. The decrease in bandgap has been reported due to codoping with Mn4+ ions in the developed phosphors. An enhancement of about 47 and 6 times in the green and red UC emission bands has been observed with the addition of Yb3+ ions. Moreover, incorporation of Mn4+ ions gives broad visible UC emission ranging from 400 nm to 900 nm. The mechanism responsible for the enhancement and broad band UC emission has been discussed on the basis of pump power dependence followed by the photon avalanche energy transfer process.

Modeling Avalanche Induced Degradation for 4H-SiC Power MOSFETs

In this letter, a model that predicates the degradation of 4H-SiC power metal-oxide-semiconductor field-effect transistors under repetitive avalanche stress is proposed. Since positive charges are injected into the gate oxide interface of the JFET region, the gate-drain capacitance $(C_{gd})$ is chosen as the targeted parameter to quantify the avalanche induced degradation. The relationship between the increment of the $C_{gd}$ and the injected charge density is calculated and validated to demonstrate the rationale of the model. It is found that the increment of $C_{gd}$ has a linear relationship with the logarithm of the total avalanche energy ( E AV) dissipated on the device. Excellent agreement is also achieved between the simulated degraded data and the measured one, further proving the accuracy of the proposed degradation model.

Investigation and Failure Mode of Asymmetric and Double Trench SiC mosfets Under Avalanche Conditions

In this article, commercially 1200-V asymmetric and double trench silicon carbide (SiC) metal-oxide-semiconductor-field-effect transistors (mosfets) from two manufacturers are investigated by experiment and finite-element simulation under single-pulse unclamped inductive switching (UIS) stress. The variation in avalanche time with mosfet avalanche energy and temperatures dependence of critical avalanche energy and maximum power dissipation are evaluated. It is found that two failure mechanisms are identified, i.e., thermal runaway and gate oxide rupture. For asymmetric trench SiC mosfets, the failure mode are all thermal runaway at various temperatures. However, the failure mode of double trench SiC mosfets is thermal runaway or gate oxide rupture, which indicates an instable avalanche robustness under UIS stress. The variations of dc parameters are recorded to evaluate external features of device failure. Furthermore, finite-element simulation is used to reveal the electro-thermal stress inside the device during avalanche. Finally, failed devices are decapsulated to verify the location of failure point from the perspective of the semiconductor die.

Verification of Single-Pulse Avalanche Failure Mechanism for Double-Trench SiC Power MOSFETs

The failure mechanism of double-trench silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) under single-pulse avalanche stress is verified. Instead of the widely reported burning out failure mechanism for planar-gate devices, double-trench SiC power MOSFETs suffer from a totally different failure mechanism, as they can only endure a much lower maximum single-pulse avalanche energy (E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">as</sub> ). It is found that during the avalanche process, obvious gate leakage current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> ) appears, which is resulted from the high impact ionization rate and high electric field along the gate trench bottom oxide interface, especially the trench corners. The I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> continuously grows along with the increase in the peak load current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> peak</sub> ), eventually leading to the breakdown of the trench bottom gate oxide under avalanche status. By increasing the value of gate resistor (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> ), the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> raises the gate-source voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> gs</sub> ) during the avalanche process, forcing the channel region in an inversion state. Part of the avalanche current is then diverted into the forward conductive current, changing the failure mode from breakdown of the gate oxide to burning out of the entire device. Moreover, the influence of different avalanche stress conditions, including the di/dt and the ambient temperature (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">a</sub> ), on the single-pulse avalanche endurance capability of double-trench SiC power MOSFETs is investigated. All the samples express a similar failure phenomenon. The higher the di/dt is, the shorter the avalanche time the device can endure. This is because the higher I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">peak</sub> results in a higher I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> during the avalanche process, leading to early failure of the gate oxide. However, the T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">a</sub> rarely influences the E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> as</sub> of the device, indicating that the single-pulse avalanche-induced failure of double-trench SiC power MOSFETs has little business with the melting of the lattice or package, demonstrating the correctness of the failure mechanism proposed in this article.

Experimental and Theoretical Demonstration of Temperature Limitation for 4H-SiC MOSFET During Unclamped Inductive Switching

This article focuses on the avalanche energy handing ability and theoretical demonstration of the avalanche failure mechanism for the SiC MOSFET by the unclamped inductive switching (UIS) test, the mathematical model, and the numerical simulation. Two evaluation methods are implemented to understand the effect of the avalanche current density and the avalanche energy on the device failure with the ambient temperature ranging from 300 to 450 K. Moreover, the thermodynamic model based on the thermal diffusion equation is developed to explore the critical temperature limitation. The avalanche capability highly depends on the dimension parameters and premature degradation points. The numerical simulation with the multicells and the real device parameters is used to reveal the electric performances of the SiC MOSFET during the UIS for the first time. At the same time, the temperatures in the SiC lattice and the metal system are precisely separated by the numerical method. The experimental results and simulation study demonstrate that the molten metal system on the surface of the SiC MOSFET induced by the local high temperature is prone to generate the thermal stresses and damage the device during the UIS transient. This failure mechanism is perfectly supported by the experimental, modeling, and numerical results.