Avalanche Capability Research Articles

SiC Super-Junction MOSFET robustness assessment and method to improve avalanche capability

In this paper, the reliability of super-junction MOSFET under single-pulse Unclamped Inductive Switching (UIS) was simulated using Sentaurus TCAD software. Through simulation of etching source metal, it was proved that the conduction of parasitic bipolar transistor in parallel multi-cell structure is the main cause of temperature concentration leading to burnout. The method of reinforcing super-junction MOSFET is proposed by using the conduction of parasitic transistors as the criterion for evaluating UIS performance. In the proposed two-layer alternating PN column stack structure, the upper PN columns have a charge imbalance structure with a higher p-column concentration than the n-column. The simulation results show that the improved structure has higher avalanche energy and wider process variation range compared to the traditional structure. Compared with the traditional device, the improved device achieves a continuous avalanche duration of 1.3 × 10−3 s and an avalanche robustness of 8.24 joules (J) when the parasitic bipolar transistor is non-conductive, significantly reducing the process difficulty by increasing the P-base concentration deviation to 5.8 × 1017 cm−3 under the same avalanche duration range.

Demonstration of High Avalanche Capability in 1200 V-Rated SiC Junction Barrier Schottky Diodes With Record Avalanche Energy Density

Demonstration of High Avalanche Capability in 1200 V-Rated SiC Junction Barrier Schottky Diodes With Record Avalanche Energy Density

Demonstration of avalanche capability in 800 V vertical GaN-on-silicon diodes

High-quality pseudo-vertical p–n diodes using a GaN-on-silicon heterostructure are reported. An optimized fabrication process including a beveled deep mesa as edge termination and reduced ohmic contact resistances enabled high on-state current density and low on-resistance. A uniform breakdown voltage was observed at 830 V. The positive temperature dependence of the breakdown voltage clearly indicates the avalanche capability, reflecting both the high material and processing quality of the vertical p–n diodes. The Baliga figure of merit, around 2 GW cm−2, which is favorably comparable to the state-of-the-art, combined with avalanche capability paves the way for fully vertical GaN-on-Silicon power devices.

Influence of Cell Design and Gate-to-Source Voltage on Avalanche Robustness of SiC MOSFET Integrated JBS Diode

In this work, 1200 V SiC JMOS devices with different Wsch (2 μm, 2.5 μm and 3 μm) are fabricated. The single unclamped inductive switching (UIS) tests under different Vgs_off (-5 V and 0 V) are carried out to investigate the avalanche capability. The avalanche robustness among various Wsch under same Vgs_off is also compared and analyzed by simulation. The different failure mechanisms between different Vgs_off are studied by failure analysis and simulation. The method of improving avalanche ruggedness of JMOS is proposed.

Avalanche capability degradation of the parallel-connected SiC MOSFETs

Silicon carbide (SiC) MOSFET chips are often connected in parallel in a module to increase the current rating. However, the current capability is degraded due to unbalanced current and temperature distributions which affect the avalanche processes particularly in extreme operating conditions. To obtain the root cause of the degradation and identify the dominant factors, single-pulse avalanche testing is carried out in this study, and TCAD simulation is used for mechanism analysis. It is revealed that electrothermal parameters have different effects on current sharing in different stages of avalanching. The corresponding failure mechanisms are analyzed, and the main cause of avalanche failure with parallel devices is found to be the difference in breakdown voltage. Device with smaller BV shares more current as well as more heat, which fails first eventually. To resolve such issues, proper device screening/paring should be carried out. The findings are helpful for a better understanding of avalanche capability degradation in parallel devices application.

Degradation and Recovery of GaN HEMTs in Overvoltage Hard Switching Near Breakdown Voltage

GaN high electron mobility transistors (HEMTs) have limited avalanche capability and usually fail catastrophically in voltage overshoot up to their dynamic breakdown voltage (BV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dyn</sub> ). This article presents the first comparative study of the parametric shift and recovery of three mainstream GaN HEMTs in repetitive overvoltage switching near their BV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dyn</sub> . In each switching cycle, a voltage overshoot up to 90% of BV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dyn</sub> was applied during the turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> process. As the switching prolongs, all devices showed shifts in threshold voltage and saturation current, and these shifts saturated in less than 1-million cycles. These shifts are believed to be induced by the trapping of the holes generated in the impact ionization (I. I.). The device's poststress recovery was found to be dominated by the hole detrapping and through-gate removal, which highly depends on the gate stack. The gate injection transistor showed a fast natural recovery benefitted from the efficient hole removal through the Ohmic gate. The hole detrapping in the Schottky-type p-gate HEMT can be described by the Poole–Frenkel emission, allowing for the accelerated recoveries at negative gate bias and high temperatures. The hole removal in the metal-insulator-semiconductor (MIS) HEMT is blocked by the gate insulator, preventing a natural recovery. The MIS-HEMT can be recovered by applying positive gate and substrate biases, which facilitate the hole recombination in the channel. This article shows the good overvoltage robustness of all three GaN HEMTs and unveils effective methods for their poststress recovery, as well as suggests the significant impacts of I. I. and hole dynamics on the overvoltage ruggedness of GaN HEMTs near BV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dyn</sub> .

GaN on Engineered Bulk Silicon Power Integration Platform With Avalanche Capability Enabled by Built-in Si PN Junctions

A GaN on engineered bulk silicon (GaN-on-EBUS) power IC platform featuring an industry-standard 200-V GaN power HEMT epi-structure has been recently demonstrated, showing effective isolation and crosstalk suppression between the high-side (HS) and low-side (LS) GaN transistors in half-bridge configuration. In this work, we scale up the vertical breakdown voltage (BV) of the GaN film on the EBUS substrate to be over 600 V. Meanwhile, the built-in back-to-back PN junctions along the trench created in the Si substrate are employed to provide an overvoltage-protection scheme through their intrinsic avalanche capability for the overlaying GaN half-bridge circuit.

GaN-on-GaN p-i-n diodes with avalanche capability enabled by eliminating surface leakage with hydrogen plasma treatment

Traditional mesa terminations require precise angle design to reduce the electric field at the edge and surface treatment to reduce etch damage. Otherwise, the device usually suffers a premature breakdown. This work proposes the use of easy-to-implement hydrogen plasma treatment to solve the premature breakdown caused by mesa and demonstrates the avalanche capability in GaN-on-GaN p-i-n diodes. The breakdown electric field when the avalanche occurred was ∼2.3 MV/cm at room temperature for a GaN drift layer with a doping concentration of ∼7 × 1015 cm−3, which is consistent with the theoretical value. The temperature coefficient of the avalanche breakdown voltage of the devices was 4.64–4.85 × 10−4 K−1. This work shows a simple and effective approach to achieve avalanche capability in vertical GaN power devices, which can serve as an important reference for the future development of efficient and robust GaN power electronics.

Edge Terminations for 4H-SiC Power Devices: A Critical Issue

Edge termination is a critical part of a power devices. Numerous edge termination types have been developed for silicon devices. Implementation of these termination architectures are not straightforward in SiC due to physical and processing specificities: lower junction depths, higher electric field, trench depth and shaping limitations, etc. Two main families of terminations are currently used in commercial devices, pure Field Guard Rings, and JTE + Rings combination. The increasing number of trench commercial devices requires new approaches based on etched rings filled with dielectrics or polysilicon. For epitaxied bipolar devices, MESA with bevel angle termination combined with JTE based architecture are also suitable. In any case, and especially regarding avalanche capability requirements, not only the termination architecture is relevant, but also the passivation type, the channel stopper design, the 3D design. As modelling using conventional tools is not fully reliable, specific complementary characterization methods are needed. For instance, micro-OBIC can be very effective to determine the electric field distribution in the periphery of the power devices.

(Invited) Breakthrough Avalanche and Short Circuit Robustness in Vertical GaN Power Devices

Power devices are highly desirable to possess excellent avalanche and short-circuit (or surge-current) robustness for numerous power electronics applications like automotive powertrains, electric grids, motor drives, among many others. Current commercial GaN power device, the lateral GaN high-electron-mobility transistor (HEMT), is known to have no avalanche capability and very limited short-circuit robustness. These limitations have become a roadblock for penetration of GaN devices in many industrial power applications. Recently, through collaborations with NexGen Power Systems (NexGen), Inc., we have demonstrated breakthrough avalanche, surge-current and short-circuit robustness in NexGen’s vertical GaN p-n diodes and fin-shape junction-gate field-effect-transistors (Fin-JFETs). These large-area GaN diodes and Fin-JFETs were manufactured in NexGen’s 100 mm GaN-on-GaN fab. The demonstrated avalanche, surge-current and short-circuit capabilities are comparable or even superior to Si and SiC power devices. Additionally, vertical GaN Fin-JFETs were found to fail to open-circuit under avalanche and short-circuit conditions, which is highly desirable for the system safety. This talk reviews the key robustness results of vertical GaN power devices and unveils the enabling device physics. Fundamentally, these results signify that, in contrast to some popular belief, GaN devices with appropriate designs can achieve excellent robustness and thereby encounter no barriers for applications in electric vehicles, grids, renewable processing, and industrial motor drives.

Tuning Avalanche Path in Vertical GaN JFETs By Gate Driver Design

The 1.2-kV vertical gallium nitride (GaN) fin-channel junction-gate field-effect transistor (JFET) has recently emerged as a promising candidate for power electronics. It is normally <small>off</small> and has a specific <small>on</small>-resistance smaller than that of 1.2-kV SiC <small>mosfets</small>. A robust avalanche capability has also been reported in vertical GaN JFETs with an avalanche current flowing through the gate. This avalanche path differs from that of power <small>mosfets</small> (via the source) and may pose challenges in gate driver reliability. This article, for the first time, demonstrates that the avalanche current in GaN JFETs can be tuned to flow through the source, by using either a <small>mosfet</small> driver with a large gate resistance or an <i>RC</i>-interface driver. These drivers turn <small>on</small> the fin channel during the device avalanche and obviate a large avalanche current into the gate driver. The carrier dynamics within the GaN JFET under the two avalanche paths have been unveiled by physics-based mixed-mode electrothermal simulations. The critical avalanche energy density in both paths was found to be comparable with the state-of-the-art SiC <small>mosfet</small>s. Additionally, the <i>RC</i>-interface driver was shown to outperform the <small>mosfet</small> driver for vertical GaN JFETs. The learning about normally <small>off</small> GaN JFETs was applied to a study of commercial normally <small>on</small> SiC JFETs. Two avalanche paths of a similar nature were observed with different gate drivers. This article provides new insights of the JFET avalanche and show the excellent robustness of the novel 1.2 kV vertical GaN JFET.

Robustness of Cascode GaN HEMTs in Unclamped Inductive Switching

Surge-energy robustness is essential for power devices in many applications such as automotive powertrains and electricity grids. While Si and SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s can dissipate surge energy via avalanche, the GaN high-electron-mobility transistor (HEMT) has no avalanche capability and withstands surge energy by its overvoltage capability. However, a comprehensive study into the surge-energy robustness of the cascode GaN HEMT, a composite device made of a GaN HEMT and an Si <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> , is still lacking. This article fills this gap by investigating the failure and degradation of 650-V-rated cascode GaN HEMTs in single-event and repetitive unclamped inductive switching (UIS) tests. The cascode was found to withstand surge energy by the overvoltage capability of the GaN HEMT, accompanied by avalanche in the Si <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> . In single-event UIS tests, the cascode failed in the GaN HEMT at a peak overvoltage of 1.4–1.7 kV, which is statistically lower than the device's static breakdown voltage (1.8–2.2 kV). In repetitive UIS tests, the device failure boundary was found to be frequency dependent. At 100 kHz, the failure boundary (∼1.3 kV) is even lower than the single-event UIS boundary. After 1 million cycles of 1.25-kV UIS stresses, devices show large but recoverable parametric shifts. All these failure and degradation behaviors can be explained by the buffer trapping in the GaN HEMT and the resulted change in its dynamic breakdown voltage. Moreover, the GaN buffer trapping is believed to be assisted by the Si <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> avalanche. An analytical model was also developed to extract the charges and losses produced in the Si avalanche in a UIS cycle. These results provide new insights into the surge-energy and overvoltage robustness of cascode GaN HEMTs.

2.8 kV Avalanche in Vertical GaN PN Diode Utilizing Field Plate on Hydrogen Passivated P-Layer

A novel edge termination method resulting in an avalanche-capable 2.8 kV vertical gallium nitride (GaN) pn diode is reported. A low transition temperature spin-on-glass (SOG) based field plate (FP) was deposited on top of the hydrogen-plasma passivated p GaN layer to achieve better electric field management. The hydrogen plasma treatment along with the field plate offered an edge termination without mesa etch that was able to mitigate the peak electric fields in the diodes. Avalanche was confirmed by the positive temperature coefficient of the breakdown voltage. Without the field plate, the breakdown voltage was recorded between 1.3 to 2.1 kV, without an avalanche behavior. The fabricated diodes exhibited a good rectifying behavior with an on-off ratio of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{{9}}$ </tex-math></inline-formula> and a specific resistance of 1.65 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{m}\Omega \cdot $ </tex-math></inline-formula> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . This work demonstrated the avalanche capability with the combination of FP and hydrogen-plasma based termination in GaN vertical pn diodes, showing a high figure-of-merit of 4.8 GW/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

The Impact of the Hexagonal and Circular Cell Designs on the Characteristics and Ruggedness for 4H-SiC MPS Diodes

In this article, SiC Merged PiN Schottky (MPS) diodes with hexagonal and circular cell designs are investigated and compared in terms of characteristics and ruggedness. It is demonstrated by experimental and simulated methods that the circular cell design brings better performance than the hexagonal one. Owing to the almost simultaneously triggering of the P+ island and the P+ ring of the circular cell under high current stress, the current distribution is more balanced, which significantly reduces forward voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{F}$ </tex-math></inline-formula> ) and lower energy-dissipated heat, and further enhances the surge current capability. Moreover, the circular shape can relieve the curvature effect and electric field crowding under reverse blocking conditions, thereby improving breakdown voltage ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BV</i> ) and avalanche capability. These results suggest that circular cell design can be employed to improve the performance and ruggedness of the SiC MPS diodes.

Impact of Negative Gate Bias and Inductive Load on the Single-Pulse Avalanche Capability of 1200-V SiC Trench MOSFETs

In this study, the single-pulse avalanche capability of two types of 1.2-kV silicon carbide (SiC) trench MOSFETs was investigated through unclamped inductive switching (UIS) testing and numerical TCAD simulation. It was found that the UIS failure mechanisms differed in the two MOSFETs. In the asymmetric trench MOSFET, the failure was caused by high temperature, which can damage the SiC layer during the UIS transient, whereas in the double-trench MOSFET, the failure was caused by a high electric field concentration at the trench gate bottom oxide, and the physical damage was confirmed by optical beam induced resistance change (OBIRCH) and scanning electron microscopy (SEM) cross-sectional analysis. In addition, the UIS-based local damage phenomenon was investigated with varying inductance. Nonuniform contact resistance may have been a cause of the avalanche current concentration.

Identification of type of threading dislocation causing reverse leakage in GaN p\u2013n junctions after continuous forward current stress

Power devices are operated under harsh conditions, such as high currents and voltages, and so degradation of these devices is an important issue. Our group previously found significant increases in reverse leakage current after applying continuous forward current stress to GaN p–n junctions. In the present study, we identified the type of threading dislocations that provide pathways for this reverse leakage current. GaN p–n diodes were grown by metalorganic vapor phase epitaxy on freestanding GaN(0001) substrates with threading dislocation densities of approximately 3 × 105 cm−2. These diodes exhibited a breakdown voltage on the order of 200 V and avalanche capability. The leakage current in some diodes in response to a reverse bias was found to rapidly increase with continuous forward current injection, and leakage sites were identified by optical emission microscopy. Closed-core threading screw dislocations (TSDs) were found at five emission spots based on cross-sectional transmission electron microscopy analyses using two-beam diffraction conditions. The Burgers vectors of these dislocations were identified as [0001] using large-angle convergent-beam electron diffraction. Thus, TSDs for which b = 1c are believed to provide current leakage paths in response to forward current stress.

Plasma Spreading Layers: An Effective Method for Improving Surge and Avalanche Robustness of SiC Devices

This article investigates the reliability issues of silicon carbide (SiC) merged p-i-n Schottky (MPS) diodes. Aiming at the current imbalance issue in surge event and electric field crowding issue under avalanche shock for MPS diodes, plasma spreading layer (PSL) structure is proposed and its performance in alleviating such issues are studied via simulation and experiments. From the simulation, the PSL structure can provide an interconnection between P+ hexagonal islands and P+ rings, and allow bipolar current to spread from the wide P+ region to the other parts of the device during the surge pulse. Under avalanche shock, the PSL structure can relieve the electric field crowding at the corners of the P+ hexagonal island/ring. In both cases, it can relieve the current crowding issue and increase the effective energy dissipating area. It is demonstrated by the experimental results that adding PSL structure can improve both surge and avalanche reliability. Different configurations of PSL (i.e., P+ cross lines and P+ diagonal lines) are studied. The P+ cross-line configuration is proved to have ~20% improvement in surge capability, and the other one achieves ~11% improvement in avalanche capability. The PSL concept can also be applied to optimizing P well/P+ layers in SiC MOSFET for its robustness enhancement.

Vertical GaN p+-n junction diode with ideal avalanche capability grown by halide vapor phase epitaxy

A vertical GaN p+-n junction diode with an ideal breakdown voltage was grown by halide vapor phase epitaxy (HVPE). A steep p+-n interface was observed even with the use of the HVPE method. No Si-accumulating layer was formed at the p+-n interface because of the continuous HVPE growth from the n-type drift layer to the p-type layer. This method provides improved electrical properties compared with the regrowth of p-type GaN layers. The minimum ideality factor of approximately 1.6 was obtained. The breakdown voltage increased from 874 to 974 V with the increase in the temperature from 25 to 200 °C, which suggests that avalanche multiplication causes the breakdown. The temperature-dependent breakdown voltage was in good agreement with the breakdown voltage calculated using the ideal critical electric field. These results indicate that HVPE is promising for the fabrication of vertical GaN power devices.

Improving avalanche robustness of SiC MOSFETs by optimizing three-region P-well doping profile

Avalanche robustness in dynamic operation is one of the main obstacles to further promote the commercialization of SiC MOSFETs. In this paper, a cell-level optimization design is proposed to suppress the avalanche failure caused by parasitic BJT activation. Several retrograde doping profiles with different thickness of lightly doping region (TLD) are designed for P-well, which is the key area affecting the avalanche failure. The analytical calculations and TCAD simulations show that as the TLD increases, the on-resistance decreases and the possibility of BJT activation increases. The TLD slightly larger than the thickness of the N+ can achieve a better avalanche capability without obvious degradation of the conduction characteristics. Besides, increasing the concentration of the retrograde P-well heavily doping region can improve the avalanche capability, but reduce the blocking voltage. This contradiction can be alleviated by adding a low-doped region at the bottom of the P-well to form a three-region P-well doping profile. This three-region P-well doping profile can achieve a significant improvement in the avalanche capability without degrading the conduction characteristic and blocking capability of the device, which provides meaningful guidance for the design of high avalanche robustness devices.

New Failure Mechanism Induced by Current Limit for Superjunction MOSFET Under Single-Pulse UIS Stress

New failure mechanism induced by current limits has been investigated for the superjunction MOSFET (SJ-MOSFET) under single-pulse unclamped inductive switching (UIS) test stress. It is found that the local charge imbalance ( Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sub> > Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</sub> ) at the chip corner produces a hotspot during the UIS test. The failure of the device induced by the hotspot depends on the magnitude of the avalanche current. For a low avalanche current, the avalanche current is redistributed from the local charge imbalance region to the charge balance region due to the lattice temperature increasing, resulting in the local heating toward the full-scale heating. However, for a high avalanche current, the negative differential resistance (NDR) effect plays a dominant role in the local charge imbalance region, decreasing the dynamic breakdown voltage (BV) sharply. Therefore, the hotspot is locked at the charge imbalance region; then, the device is destroyed in a short time. Finally, an SJ-MOSFET with more p-type charges at the chip corner is produced to improve the avalanche capability relating to the current limit, also verifying the mechanism analysis.