Automatic Gain Control Loop Research Articles

Evolution of and Perspectives on Differential‐Pair‐Based CMOS Variable Gain Amplifiers With Linear‐in‐Decibel Gain Control: A Tutorial

ABSTRACTA variable gain amplifier (VGA) is an essential building block used in the automatic gain control (AGC) loop to provide a continuous, adjustable gain for the signal strength. To maintain the stability and consistency of the AGC loop, it is necessary to ensure that the gain of the VGA has an accurate dB‐linear characteristic. This tutorial provides a detailed overview of the development of dB‐linear VGAs based on differential pair structures over recent years. We categorize various VGA cells based on differential pair structures, analyze their operating principles, and explain the key features of each topology. Based on observation and extraction of the dB‐linear implementation schemes used by these VGAs, we summarize three basic methods for achieving dB‐linear gain control. We also discuss specific methods for realizing the exponential function, using a true exponential and a mathematical approximation, and present the different types of approximation functions adopted in the works described here. Considerations in regard to the tuning range, gain error, bandwidth, linearity, process‐temperature robustness, and circuit simplicity are also discussed. Finally, we draw comparisons and give perspectives for future dB‐linear VGAs.

A novel programmable gain control low noise amplifier (PGCLNA) design for automatic gain control loop in BLE applications

Bluetooth low energy (BLE) is a widely used short-range communication protocol and BLE receivers frequently encounter transient high-power RF (radio frequency) signals from antennas, leading to receiver saturation. To address this issue, this work proposes a 2.4 GHz programmable gain control low-noise amplifier (PGCLNA), which is a key element in an automatic gain control (AGC) system for BLE receiver applications. The proposed PGCLNA achieves discrete levels of gain using the g m -boosting technique by splitting the negative feedback. The proposed circuit is simulated in UMC 180 nm technology and the maximum gain achieved is 41.4 dB, with a step decrease of 15 dB in discrete levels. The gain variations do not degrade the performance of S11, which is always less than -16 dB. The noise figure (NF) is always minimum of 5.5 dB and in high gain mode, the minimum value of NF is 1.82 dB. The third-order intercept point (IIP3) is −7.621 dBm in the best circumstances and always remains above −10.69 dBm. These results are achieved by utilising 5.4 mW power at 1.8 V of supply voltage. The circuit occupies an area of 732 μm × 771 μm. The proposed PGCLNA design offers a solution to accommodate a wide range of input signals in BLE receivers, excellent gain control, low noise and robust performance characteristics, making it an essential component in an AGC system for BLE receiver applications.

A 56‐GBaud lumped linear push–pull driver for Mach–Zehnder modulator in 130‐nm SiGe technology

AbstractA fully differential lumped linear driver for Mach–Zehnder modulator has been presented and assessed in 130‐nm SiGe BiCMOS technology. Multitopology peaking techniques, especially T‐coil peaking method, have been employed to flatten the frequency response and increase the bandwidth. Degeneration resistors have been used to enhance circuit linearity. Simultaneously, improvements have been made to the output stage of the conventional single emitter follower push–pull) circuit to enhance the output eye diagram quality at higher transmission rates. The fabricated driver achieved a differential gain of 16.2 dB with a bandwidth of over 50 GHz, corresponding to a fixed output swing of over 3.2 Vppd within the automatic gain control loop. Time domain measurements, limited in speed by the measurement setup, reported a data rate up to 56 Gb/s none return to zero and 40‐GBaud 4‐levels pulse amplitude modulation with a bit error rate less than 10−12.

Coupled Double Closed-Loop Control for an MEMS Resonant Accelerometer.

There is mutual coupling between amplitude control and frequency tracking control in the closed-loop control of micromechanical resonant sensors, which restricts sensor performance. This paper introduces the principle of an in-plane vibration micromechanical resonant accelerometer with electrostatic stiffness. The characteristic parameters of the microaccelerometer were obtained through computer-aided dimension measurement and an open-loop frequency sweep test of the fabricated microstructure. An accurate numerical model was established based on the accelerometer’s dynamic principle and characteristic parameters. We established the double closed-loop driving analysis model of amplitude automatic gain control and resonant frequency phase-locked tracking. We used the averaging method to analyze the steady-state equilibrium point and the stable condition. We concluded that the integral coefficient can improve the startup overshoot when the amplitude automatic gain control loop satisfies the stability condition. Under the constraint of frequency tracking, the sizeable coefficient of the integrator can improve the system instability of the amplitude control loop. The theoretical analysis and simulation were helpful in the design and debugging of the system circuit.

Design of an automatic gain control loop for high speed communication

AbstractThis paper presents the design of an automatic gain control (AGC) loop for high‐speed communication systems, which can be used in wired, wireless, or optical receiver. The design is performed in 130 nm SiGe BiCMOS technology. A Gilbert cell‐based variable gain amplifier is designed, which shows approximately linear gain control with respect to the gain control voltage. The variable gain amplifier is followed by two fixed gain cascode amplifiers. Then, a full wave rectifier‐based peak detector is designed and analyzed. To reduce the peak detector error, a compensation technique is applied. Finally, an operational amplifier is designed, which is used as voltage adder and comparator. The designed AGC loop is simulated with sinusoidal and pseudorandom binary sequence (prbs) input signal with high frequency signal of 1 to 30 GHz. The simulation results of the AGC loop show that a gain tuning range of 47 dB (−7 to 40 dB) is obtained in this design. It is also seen that the reference signal can be varied from 50 to 200 mV. This AGC works in the input voltage signal range between 3 mV peak and 230 mV peak, and the power dissipation of is 79 mW.

Phase noise modelling of MEMS resonant accelerometer with non-AGC-driven circuit

Phase noise is an essential performance indicator for microelectromechanical system (MEMS) resonant accelerometers. The optimal resolution achievable is limited by the close-to-the carrier phase noise resulting from the modulation of noise sources by the mechanical resonator and driving circuit. Compared with the frequently used automatic gain control (AGC) circuit, the non-AGC scheme is more concise and can avoid the additional frequency flicker noise and 1/f 5 phase noise introduced by the AGC module. Although the mechanisms of these two kind of control loops are well-known by the communities, the phase noise modelling study on the non-AGC loop, especially compared with that of AGC loop is insufficient. This paper established a phase noise model for the AGC and non-AGC closed loop circuit of MEMS resonant accelerometer. The model includes the effects of resonator thermal noise, random loading noise of proof masses, front-circuit noise, comparator noise, AGC noise and amplitude stiffness coupling on the output noise spectrum of the resonant accelerometer. This paper carries the noise analysis through a behaviour level simulation with Simulink. The measured frequency power spectral density and Allan variance are very close to the theoretical predictions, which verifies the effectiveness of the phase noise model. The test results show that the white noise and the bias instability of the silicon resonant accelerometer are 837 ng (√Hz)−1 and 140 ng respectively, which are in good agreement with the model prediction results.

A large gain variable range, high linearity, lownoise, low DC offset VGAs used in BD system

In this paper, a large gain variable range, high linearity, low noise, low DC offset VGAs with a simple gain-dB variable circuit are introduced. In the VGAs chain, the last and the first VGAs employ Bipolar transistors, to improve the linearity and noise characteristics. And the middle three stages VGAs employ MOS transistors. The whole circuitry is designed in 0.35um BiCMOS process, including variable gain amplifiers (VGAs) , fixed gain amplifiers , gain control and DC offset cancellation parts. The automatic gain control loop (AGC) provides a process independent gain variable range of 60dB (including 50dB gain-dB-linearity variable range), with a 200us loop lock time, the VGAs provide a 73dB largest gain, the THD is less than 1% at a 1V(P-P) output level; the equivalent output integral noise is 0.011v/√hz@20MHz bandwidth. The whole area is 1173um*494 um, and the power is 7.1mA at 3.3V signal supply voltage.

Error Performance of Subsampling Digital Power Estimation for Integrated Receivers

Estimation of signal power levels at the output of integrated receiver building blocks is a vital function as the block voltage or power gains are set based on sensed power levels to maintain constant levels at block outputs in the receiver chain. RF and IF level real-time gain settings are determined with Automatic Gain Control (AGC) loops. AGC loop circuit topologies are usually based on analog detection circuits. These analog power detection circuits are based on techniques such as envelope detection, and logarithmic amplification usually accompanied by severe accuracy issues such as Process, Voltage and Temperature (PVT) spreads preventing correct gain adjustments. Adopting a dominantly digital approach to detect the signal power would ensure a significant reduction in PVT spreads. This work presents a review of the subsampling digital power estimation to create low power digital power estimations alternative to analog methods. The simulations of the method are applied to an AM and a 64-QAM signal. Simulation results show that the power estimation error is within the acceptable level of [Formula: see text][Formula: see text]dB.

A 20-Gb/s wideband AGC amplifier with 26-dB dynamic range in 0.18-μm SiGe BiCMOS

This paper presents a 20-Gb/s automatic gain control (AGC) amplifier in a 0.18-μm SiGe BiCMOS for high-speed applications. The proposed AGC amplifier compactly consists of a folded Gilbert variable-gain amplifier (VGA), a post amplifier (PA), a 50-Ω output buffer, and AGC loop including an open-loop peak detector (PD), a RC low-pass filter (LPF), and an error amplifier (EA). The AGC amplifier achieves the broadband characteristic by utilizing inductive peaking and capacitive degeneration as well as fT-doubler techniques to overcome the large parasitic capacitances. The proposed AGC circuits together with a linear VGA exhibits a wide gain control range of 45 dB for the received signal strength indication (RSSI). The measured AGC amplifier achieves a maximum gain of 21 dB and a -3-dB bandwidth (BW) of 20.6 GHz, which can support up to 25.4-Gb/s data rate. For the pseudorandom bit sequence (PRBS) length 231–1 with a bit-error rate (BER) of 10−12 at 20 Gb/s, the measured input dynamic range is 26 dB (20–400mVpp) and the peak-to-peak data jitter is less than 8 ps. The AGC amplifier consumes a power of 160 mW from a 3.3-V supply voltage and occupies an area of 850 μm × 850 μm.

PLL-based nanoresonator driving IC with automatic parasitic capacitance cancellation and automatic gain control

This paper presents a phase-locked loop (PLL) based resonator driving integrated circuit (IC) with automatic parasitic capacitance cancellation and automatic gain control. The PLL consisting of a phase frequency detector (PFD), a loop filter, and a voltage-controlled oscillator (VCO) makes the driving frequency to be locked at the resonant frequency. The resonator is modeled by Butterworth–Van Dyke equivalent circuit model with motional resistance of 72.8 kΩ, capacitance of 6.19 fF, inductance of 79.4 mH, and parasitic parallel capacitance of 2.59 pF. To mitigate the magnitude and phase distortion in the resonator frequency response, it is necessary to compensate for the parasitic capacitance. The proposed automatic parasitic capacitance cancellation loop is operated in the open-loop mode. In the automatic parasitic capacitance cancellation phase, the outputs of the transimpedance amplifier (TIA) at the lower and higher frequency than the resonant frequency (VH and VL), are compared, and the programmable compensation capacitor array matches the VH and VL using binary-searched algorithm to cancel the parallel parasitic capacitance. The automatic gain control (AGC) loop keeps the oscillation at the suitable amplitude, and the AGC output can be used as a measurement of the motional resistance. The AGC loop is also digitally controlled. The proposed resonator driving IC is designed in a 0.18-μm bipolar complementary metal oxide semiconductor double-diffused metal oxide semiconductor (BCDMOS) process with an active area of 3.2 mm2. The simulated phase noise is −61.1 dBc/Hz at 1 kHz and the quality factor ( Q-factor) is 59,590.

A Sub-1-GHz Band High-Dynamic-Range Receiver With Integrated Self-Adaptive Multipart AGC Loops

This article presents a fully differential high-dynamic-range direct-conversion receiver for sub-1-GHz band applications in a 180-nm CMOS technology. The integrated self-adaptive multipart automatic gain control (AGC) loops are designed to cope with large input signal. In the radio frequency (RF) domain, a gain-adjustable noise-canceling balun low-noise amplifier (LNA) and a high-linearity RF variable gain amplifier (VGA) are co-designed to keep a steady differential output power for the mixer stage. In baseband (BB), a novel gain distribution method is proposed to protect BB circuits from saturation. To prove the concept, one of the most typical and strict application scenarios in the sub-1-GHz band, digital television (DTV) standard, is analyzed and chosen as the design target. The receiver achieves a noise figure (NF) of 3.6–4.6 dB in the ultrahigh-frequency (UHF) band. A wide gain tuning range of 128.8 dB is realized in this work, featuring fully integrated AGC loops. The programmable bandwidth of the low-pass filter (LPF) can be adjusted from 1 to 4 MHz, supporting 2-/6-/7-/8-MHz signal channels. The maximum in-band third-order input-referred intercept point (IIP3) is 10 dBm under the conversion gain of 0 dB. The receiver consumes 49.56 mA from a 1.8-V voltage supply and occupies an area of 3.56 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Control of Vibratory MEMS Gyroscope With the Drive Mode Excited Through Parametric Resonance

Abstract In this paper, we present a control strategy for a micro-electro-mechanical gyroscope with a drive mode excited through parametric resonance. The reduced order two degrees-of-freedom model of the device is built, and the drive mode control is implemented using phase-locked loop (PLL) and automatic gain control (AGC) loop. A sense mode vibration control algorithm is developed as well for enhanced sensor performance. The analysis of the drive mode control loops is conducted using the multiple scales method. The robustness of the suggested control loops to parameters perturbation is demonstrated using the model. A simplified linear model of the control loops is shown to predict the device behavior with good accuracy.

A 7-nm FinFET CMOS PLL With 388-fs Jitter and −80-dBc Reference Spur Featuring a Track-and-Hold Charge Pump and Automatic Loop Gain Control

This article presents a phase-locked loop (PLL) design that overcomes design challenges imposed by FinFET CMOS nodes, notably high gate resistance and middle-end-of-line parasitics. We propose a track-and-hold charge pump (THCP) and an automatic loop gain control, which not only overcome these challenges but also improve the PLL jitter and reference spur performance. The proposed THCP achieves −115-dBc/Hz in-band phase noise while consuming only $53~\mu \text{W}$ , which is less than 1% of total PLL power consumption. The ring-based PLL achieves both 388-fsrms integrated jitter and reference spurs at −80 dBc. At 4.0 GHz, this PLL consumes 5.9 mW from a 0.9-V supply, translating to a figure of merit of −240.5 dB. The PLL is fabricated in the TSMC 7-nm FinFET CMOS technology.

A Fully Integrated K-Band Dual Down-Conversion Receiver for Radar Applications in 90 nm CMOS

A fully integrated K-band dual down-conversion receiver for phased array radar applications in 90 nm CMOS is presented. The receiver utilizes the dual down-conversion architecture to achieve superior performance. The integrated 1.15 GHz image-rejection filter (IRF) provides enough wideband (22 MHz) image rejection ratio at 140 MHz offset before the second down-conversion by utilizing the Q-enhancing and frequency staggering techniques to compensate the component loss. The low noise amplifier realizes the single-to-differential-ended conversion at the input with a transformer and achieves good common-mode rejection. The 70 MHz intermediate frequency baseband consists of two cascaded 3rd-order band-pass active RC filters (BPFs) and one automatic gain control (AGC) loop, with the integrator frequency compensation technique to lower down the requirements on the embedded Op-Amps. Two phase-locked loop (PLL) frequency synthesizers are integrated to provide the local oscillation (LO) signals for the down-conversions, where the matching of the charge-pump is improved by adding one extra current compensation branch. The measurements of the prototype show that the receiver converts the targeted mm-wave signal to 70 MHz intermediate frequency while achieving 8.3 dB noise figure (NF), 51-95 dB variable gain range and >45 dB image rejection ratio at 140 MHz offset with >22 MHz signal bandwidth. The receiver draws 74 mA current (excluding 2 PLLs) from the 1.2 V power supplies and occupies a core area of 4.58 × 0.53mm 2 (excluding 2 PLLs).

A Highly Reconfigurable Bit-Level Duty-Cycled TRF Receiver Achieving −106-dBm Sensitivity and 33-nW Average Power Consumption

This letter presents a reconfigurable wake-up receiver, which obtains −106-dBm sensitivity with power consumption as low as 33 nW. Bit-level duty cycling provides 68-dB RF gain at sub- $\mu \text{W}$ average power consumption, improving sensitivity over other sub- $\mu \text{W}$ receivers. The receiver rejects interference using a compact RF MEMS filter and a fully automatic gain and offset control loop. Digital tuning of dc power, latency, and sensitivity provides high levels of flexibility to enable a wide variety of applications, spanning latency from 240 ms to 5 s, dc power consumption from 288 nW to 33 nW, and sensitivity from −106 dBm to −103 dBm. Three example modes are presented to highlight the range of this tuning.

A 0.25-dB-Step, 68-dB-Dynamic Range Analog Baseband With Digitally Assisted DCOC and AGC for Multi-Standard TV Applications

This brief presents a low noise, high dynamic range (DR), high linearity, and high selectivity analog baseband (BB) for multi-standard TV applications. A customized sixth-order low pass filter with two additional zeroes Chebyshev-I filter is adopted to enhance the average adjacent channel rejection (ACR) and the attenuation at 5.25 MHz, and a novel programmable gain amplifier (PGA) realizes accurate gains with a fine-tuning gain step of 0.25 dB. The digitally assisted real-time dc offset cancellation (DCOC) loop can prevent the BB chain from saturation robustly with a low residual output dc offset voltage (DCOV) and an extremely low cut-off frequency. The digitally assisted complementary cumulative distribution function (CCDF)-based on-chip automatic gain control (AGC) loop implements reliable amplitude control for digital TV signals with a large peak to average power ratio (PAPR). The BB chain fabricated in a 0.18 ${\mu }\text{m}$ CMOS process occupies an area of 1.2 mm2 and consumes a current of 21.3 mA from 1.8-V supply including the output buffer. It achieves a maximum gain of 62 dB and a DR of 68 dB with 0.25 dB minimum step. The attenuation at 5.25 MHz is 48.6 dB and the average ACR is 38.2 dB. The measured equivalent input-referred noise voltage is 22 ${\mathrm{ nV/}}\sqrt {\mathrm{ Hz}} $ , out-of-band IIP3 of 37.61 dBV, and out-of-band IIP2 of 77.19 dBV at 56 dB gain. The residual output DCOV is less than 5 mV and the minimum 3 dB cut-off frequency is 100 Hz when BB operates in the maximum gain of 62 dB.

A 19-GHz Pulsed-Coherent ToF Receiver With 40-$\mu$ m Precision for Laser Ranging Systems

This letter presents a pulsed-coherent time-of-flight (ToF) receiver for a laser ranging system implemented in 28-nm CMOS process. The prototype is designed at 19-GHz carrier frequency with 6.8-ns pulsed modulation. A segmented coarse-fine ToF measurement is adopted to achieve high resolution and fast acquisition. The coarse ToF is recorded by detecting the pulse's edge whereas the fine measurement is measured by coherent detection. The proposed post-edge detection with automatic gain control loop provides better suppression of walk error from 600 to 26 ps as compared to the rising-edge detection. Also, phase-invariant variable-gain amplifiers provide a low phase error of <; ±1° across gain settings with 60-dB dynamic range. This letter can, based on the timing accuracy, achieve 40-μm precision with 1-MHz sampling rate.

34-GBd Linear Transimpedance Amplifier for 200-Gb/s DP-16-QAM Optical Coherent Receivers

High spectral efficiency offered by the coherent optical communication links makes them attractive for the next-generation optical communication links. Using advanced modulation schemes such as dual-polarization quadrature-amplitude modulation (DP-QAM) data rates beyond 200 Gb/s can be achieved. A key component of such links is the wide-bandwidth and high-linearity coherent optical receiver. In this paper, we present a fully differential (FD) optical receiver architecture consisting of a variable-gain transimpedance amplifier (VG-TIA) followed by a VG amplifier (VGA). The proposed optical receiver employs a dual-feedback automatic gain control (AGC) loop that controls both the front-end VG-TIA and the following VGA to achieve both low-noise and high-linearity operation. A new photodiode (PD) dc current cancellation scheme is developed and implemented for the full differential front-end TIA. A prototype dual-TIA chip is fabricated in a 0.13- $\mu \text{m}$ SiGe BiCMOS process. The presented TIA achieves 20-pA/ $\sqrt {\text {Hz}}$ input-referred noise (IRN) density, 27-GHz, 3-dB bandwidth, and 1.5% total harmonic distortion (THD) at 1-mApp input PD current and 500-mVpp output voltage swing. This enables the 34-GBd operation with the bit error rate (BER) of $10^{-10}$ and $5.4\times 10^{-4}$ using DP-QPSK and DP-16-QAM formats at optical signal-to-noise ratios (OSNRs) of 25 and 30 dB, respectively, demonstrating the 100- and 200-Gb/s single wavelength optical coherent receiver operation. The dual-TIA chip occupies an area of $1.4\,\,\text {mm}\times 1.6$ mm and consumes 313 mW per channel at 34 GBd from a 3.3-V supply.

A 79-dB SNR 1.1-mW Fully Integrated Hearing Aid SoC

For low-power hearing aid device application, a fully integrated optimized hearing aid SoC structure is proposed in this paper. The SoC consists of high-resolution, low-power analog front-end (AFE), time-division-multiplexed power-on-reset circuit, charge pump, digital signal processing (DSP) platform, and Class-D amplifier. A novel peak-statistical algorithm is proposed to track signal amplitude and adjust automatic gain control loop gain precisely. A comparative DWA is applied to break the correlation of in-band tone and sequential selection scheme, which realizes second-order noise shaping and suppresses harmonic effectively. The SoC has been implemented with 0.13 µm CMOS process. By measurement, it shows that the peak signal-to-noise ratio (SNR) of AFE is 82.6 dB and peak SNR of Class-D amplifier is 79.8 dB. Also, three main algorithms of wide dynamic range compression, noise reduction, and feedback cancelation are executed through DSP platform. With 1 V supply voltage, total SoC power is 1.1 mW and core area is 9.3 mm2. Based on our SoC, a hearing aid device prototype is produced that shows its great potential for mass manufacture in the future.

Nonlinear Modelling of Automatic Gain Control Loops Considering Loop Dynamics and Stability

This work presents modelling aspects of automatic gain control (AGC) loops based on linear-in-dB variable gain amplifiers (VGAs). In these loops, the VGA control voltage is also an excellent received signal strength indicator (RSSI). The VGA gain is however nonlinearly related to the control voltage. Moreover, VGAs and detectors undergo nonlinear compression under high input amplitudes during settling transients. In this work, these effects are captured by a nonlinear model based on simple and readily available components from the “analogLib” and “functional” libraries in CADENCE design environment making it very easy and fast to build and simulate. The model is capable of verifying the AGC loop stability and capturing the loop dynamics with high accuracy compared to time consuming circuit level simulations. This provides insights into system level parameters such as AGC loop bandwidth, phase margin, settling time as well as estimating the AGC range and RSSI voltage vs. input power. Measurement results from a fabricated AGC prototype are in good agreement with simulation and modelling results thus validating the proposed modelling approach.