A 7-nm FinFET CMOS PLL With 388-fs Jitter and −80-dBc Reference Spur Featuring a Track-and-Hold Charge Pump and Automatic Loop Gain Control

Abstract

This article presents a phase-locked loop (PLL) design that overcomes design challenges imposed by FinFET CMOS nodes, notably high gate resistance and middle-end-of-line parasitics. We propose a track-and-hold charge pump (THCP) and an automatic loop gain control, which not only overcome these challenges but also improve the PLL jitter and reference spur performance. The proposed THCP achieves −115-dBc/Hz in-band phase noise while consuming only $53~\mu \text{W}$ , which is less than 1% of total PLL power consumption. The ring-based PLL achieves both 388-fsrms integrated jitter and reference spurs at −80 dBc. At 4.0 GHz, this PLL consumes 5.9 mW from a 0.9-V supply, translating to a figure of merit of −240.5 dB. The PLL is fabricated in the TSMC 7-nm FinFET CMOS technology.