A 387.6fs Integrated Jitter and -80dBc Reference Spurs Ring based PLL with Track- and-Hold Charge Pump and Automatic Loop Gain Control in 7nm FinFET CMOS

Abstract

This paper presents a phase-locked loop that employs a track-and-hold charge pump and automatic loop gain control to enhance the jitter and spur performance against PVT variations. The chip is fabricated in 7nm FinFET technology. The proposed track-and-hold charge pump achieves $\lt -115$dBc/Hz in-band noise and consumes $53 \mu \mathrm{W}$ from a 0.9V supply. The ring-based phase-locked loop achieves 387.6fs rms integrated jitter and -80dBc reference spurs, and consumes 5.9mW from a 0.9V supply at 4GHz. This translates to a figure-of-merit (FOM) of -240.5dB.