Au Bumps Research Articles

Failure Analysis on Abnormal Cracking of Flip-Chip Au Bumps During the High Temperature and Humidity Testing

Failure Analysis on Abnormal Cracking of Flip-Chip Au Bumps During the High Temperature and Humidity Testing

Thermal Analysis of Flip-Chip Bonding Designs for GaN Power HEMTs with an On-Chip Heat-Spreading Layer

In this work, we demonstrated the thermal analysis of different flip-chip bonding designs for high power GaN HEMT developed for power electronics applications, such as power converters or photonic driver applications, with large gate periphery and chip size, as well as an Au metal heat-spreading layer deposited on top of a planarized dielectric/passivation layer above the active region. The Au bump patterns can be designed with high flexibility to provide more efficient heat dissipation from the large GaN HEMT chips to an AlN package substrate heat sink with no constraint in the alignment between the HEMT cells and the thermal conduction bumps. Steady-state thermal simulations were conducted to study the channel temperatures of GaN HEMTs with various Au bump patterns at different levels of current and voltage loadings, and the results were compared with the conventional face-up GaN die bonding on an AlN package substrate. The simulations were started from a single finger isolated HEMT cell and then extended to multiple fingers HEMT cells (total gate width > 40 mm) to investigate the "thermal cross-talk" effect from neighboring devices. Thermal analysis of the GaN HEMT under pulse operation was also performed to better reflect the actual conditions in power conversion or pulsed laser driver applications. Our analysis provides a combinational assessment of power GaN HEMT dies under a working condition (e.g., 1MHz, 25% duty cycle) with different flip chip packaging schemes. The analysis indicated that the channel temperature rise (∆T) of a HEMT cell in operation can be reduced by 44~46% by changing from face-up die bonding to a flip-chip bonding scheme with an optimized bump pattern design.

Height Uniformity Simulation and Experimental Study of Electroplating Gold Bump for 2.5D/3D Integrated Packaging.

With the rapid development of nano/micro technology for commercial electronics, the typical interconnection method could not satisfy the high power-density packaging requirement. The 2.5D/3D integrated packaging was seen as a promising technology for nano/micro systems. The gold (Au) bump was the frequently used bonding method for these systems because of its excellent thermal, electric, and mechanical performance. However, relatively little work has been performed to analyze its height uniformity. In this study, the simulation and experimental methods were used to analyze the Au bump height uniformity. Firstly, the electroplating process of Au bump under different flow field parameters was simulated by COMSOL software. The simulated results indicated that the Au+ concentration polarization was the significant reason that caused the non-uniform distribution of Au bump along the wafer radius. Meanwhile, the flow field parameters, such as inlet diameter, inlet flow, titanium (Ti), wire mesh height, and Ti wire mesh density, were optimized, and their values were 20 mm, 20 L/min, 12 mm, and 50%, respectively. Subsequently, the Au bump height uniformity under different current densities was analyzed through an experimental method based on these flow field parameters. The experimental results showed that the increases of current density would decrease the Au bump height uniformity. When the current density was 0.2 A/dm2, the average height, range, and deviance values of Au bump were 9.04 μm, 1.33 μm, and 0.43 μm, respectively, which could reach the requirement of high density and precision for 2.5D/3D integrated packaging.

Development of 3D Wafer Level Hermetic Packaging with Through Glass Vias (TGVs) and Transient Liquid Phase Bonding Technology for RF Filter.

The development of 5G mobile communication created the need for high-frequency communication systems, which require vast quantities of radio frequency (RF) filters with a high-quality factor (Q) and low inband losses. In this study, the packaging of an RF filter with a through-glass via (TGV) interposer was designed and fabricated using a three-dimensional wafer-level package (3D WLP). TGV fabrication is a high-yielding process, which can produce high precision vias without masking and lithography and reduce the manufacturing cost compared with the through silicon via (TSV) solution. The glass interposer capping wafer contains Cu-filled TGV, a metal redistribution layer (RDL), and the bonding layer. The RF filter substrate with Au bump is bonded to the capping wafer based on Au-Sn transient liquid phase (TLP) bonding at 280 °C with a 40 kN (approximately 6.5 MPa) bonding force. Experimental results show that shear strengths of approx. 54.5 MPa can be obtained, higher than the standard requirement (~6 MPa). In addition, a comparison of the electrical performance of the RF filter package after the pre-conditional level three (Pre-Con L3) and unbiased highly accelerated stress (uHAST) tests showed no difference in insertion attenuation across the passband (<0.2 dB, standard value: <1 dB). The final packages passed the reliability tests in the field of consumer electronics. The proposed RF filter WLP achieves high performance, low cost, and superior reliability.

Heterogeneously integrated membrane III-V compound semiconductor devices with silicon photonics platform

Silicon photonics is a key technology for constructing large-scale photonic integrated circuits (PICs) because it enables large-scale wafer processes with high uniformity and quality. To further improve device characteristics, heterogeneous integration of III-V compound semiconductors that provide optical gain, a high modulation efficiency, and optical non-linearity is desired. This paper describes the heterogeneous integration of membrane III-V compound semiconductor photonic devices that have a similar structure including thickness and refractive index. These devices provide efficient optical coupling with a Si waveguide using a simple taper waveguide structure. If the total thickness of the film structure is designed to be less than the critical thickness (calculated to be 430 nm for fabrication conditions such as bonding and growth temperatures), high-quality epitaxial layers can be grown on a thin InP layer directly bonded to the Si substrate. Therefore, regrowth techniques are employed on bonded InP layer on SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si substrate. We fabricate two kinds of laser-integrated Mach-Zehnder modulators using epitaxial regrowth on Si substrates. One uses Si phase modulators, and the other uses InP-based modulators. A micro-transfer-printing technology is also important when the number of III-V devices is relatively small. Furthermore, the micro-transfer-printing technology enables devices to be selected that meet the required characteristics before integration. For this purpose, we try to integrate a membrane laser on a Si substrate, in which the membrane laser is fabricated on InP substrate. The device shows a threshold current of 0.8 mA when the active region length is 140 μm. Finally, we briefly describe a transmission module, in which directly modulated membrane lasers and electronic drivers are integrated by flip-chip bonding through Au bumps. To reduce power consumption, it is important to design driver circuits that incorporate semiconductor lasers as electronic components. We demonstrate a 2-channel 53-Gbit/s 4-level pulse amplitude modulation (PAM4) transmitter front-end consisting of a 2-channel PAM4 shunt laser driver and 2-channel O-band directly modulated membrane lasers. The total power consumption is only 60.7 mW, resulting in 0.57 mW/Gbit/s.

Correction to: Design of a GaN-based flip chip light emitting diode (FC-LED) with Au bumps &amp; Thermal analysis with different sizes and adhesive materials for performance considerations

Correction to: Design of a GaN-based flip chip light emitting diode (FC-LED) with Au bumps &amp; Thermal analysis with different sizes and adhesive materials for performance considerations

Design of a GaN-Based Flip Chip Light Emitting Diode (FC-LED) with au Bumps &amp; Thermal Analysis with Different Sizes and Adhesive Materials for Performance Considerations

Design of a GaN-Based Flip Chip Light Emitting Diode (FC-LED) with au Bumps &amp; Thermal Analysis with Different Sizes and Adhesive Materials for Performance Considerations

Fabrication and Packaging of CMUT Using Low Temperature Co-Fired Ceramic.

This paper presents fabrication and packaging of a capacitive micromachined ultrasonic transducer (CMUT) using anodically bondable low temperature co-fired ceramic (LTCC). Anodic bonding of LTCC with Au vias-silicon on insulator (SOI) has been used to fabricate CMUTs with different membrane radii, 24 µm, 25 µm, 36 µm, 40 µm and 60 µm. Bottom electrodes were directly patterned on remained vias after wet etching of LTCC vias. CMUT cavities and Au bumps were micromachined on the Si part of the SOI wafer. This high conductive Si was also used as top electrode. Electrical connections between the top and bottom of the CMUT were achieved by Au-Au bonding of wet etched LTCC vias and bumps during anodic bonding. Three key parameters, infrared images, complex admittance plots, and static membrane displacement, were used to evaluate bonding success. CMUTs with a membrane thickness of 2.6 µm were fabricated for experimental analyses. A novel CMUT-IC packaging process has been described following the fabrication process. This process enables indirect packaging of the CMUT and integrated circuit (IC) using a lateral side via of LTCC. Lateral side vias were obtained by micromachining of fabricated CMUTs and used to drive CMUTs elements. Connection electrodes are patterned on LTCC side via and a catheter was assembled at the backside of the CMUT. The IC was mounted on the bonding pad on the catheter by a flip-chip bonding process. Bonding performance was evaluated by measurement of bond resistance between pads on the IC and catheter. This study demonstrates that the LTCC and LTCC side vias scheme can be a potential approach for high density CMUT array fabrication and indirect integration of CMUT-IC for miniature size packaging, which eliminates problems related with direct integration.

Electroless Under Bump Metallurgy Deposition on Batches of Singulated Semiconductor Die

Multi project-wafers (MPWs) offer cost-effective options for fabrication of application specific integrated circuits (ASICs) produced for entities not requiring a large volume of die from a dedicated full wafer run at an advanced semiconductor foundry. MPWs consist of a mixture of different devices shared on a single wafer; thereby reducing cost of processing by allowing the purchase of real estate allotted to each device. This practice is advantageous for those in academia or government that often only require small quantities of devices for research or niche applications. With many teams investing in a single wafer run, strict design rules must be followed on these microelectronic chips. In particular, the metal used in the final routing layer must be AlCu. This AlCu metallization is not compatible with solder connections for flip chip bonding applications because solder is unable to wet AlCu. To allow MPW die integration with flip chip bonding applications, a solder compatible under bump metallization (UBM) must be deposited on top of the AlCu. This UBM deposition can be achieved through physical vapor deposition and subsequent electrolytic plating into a photolithography defined plating mold. Unfortunately, photolithographic processes are only compatible with full wafers and not with singulated die. This leaves electroless deposition methods such as immersion tin or zinc followed by electroless nickel, electroless palladium, immersion gold (ENEPIG) or electroless nickel and immersion gold (ENIG) as the only options for depositing a wettable UBM on MPW die. Electroless deposition can be performed with a single die at a time, however this process is not well suited for manufacturing. In this work, we have developed a scheme for batch level UBM deposition on singulated semiconductor die by coupling temporary bonding with electroless deposition. A unique batch approach is proposed to electrolessly deposit UBM to terminal AlCu on MPW die. Preliminary Si sidewall passivation is used to eliminate metallization of unintended surfaces in subsequent steps. Temporary custom fixturing onto a carrier substrate is leveraged allowing a variety of devices to be processed like a full wafer, establishing feasibility for industrial scaling. The bulk aluminum oxide is then solubilized by chemical etching and replaced by reduction of Sn as a base layer for ENIG and ENEPIG processes as seen in Figure 1. After metal deposition, devices are liberated from the temporary mounting substrate making them ready for flip chip bonding. Due to creating an UBM through electroless processes, options for interposer bumps are limited and outlined in Figure 2. Solder bonds from Cu pillars topped with SnAg or electroplated with either AuSn or SnAg allow a reflow solder attachment to complete electrical contact between the two chips. Electroplated Au bumps allow for a thermocompression bond to be made between the two chips. Both methods have benefits based on circumstance. Reflow solder is advantageous for fragile chips that cannot withstand the high pressure associated with thermocompression. Cu pillars are also attractive for RF devices in that Cu offers reduced electrical parisitics. Thermocompression is advantageous because it does not require high level of uniformity in the final Au bump. In this presentation, we will provide details on the passivation, batch level handling process, uniformity, and yield statistics for the electroless deposition. Supported by the Laboratory Directed Research and Development program at Sandia National Laboratories, a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525. Figure 1

3-Axis Fully-Integrated Capacitive Tactile Sensor with Flip-Bonded CMOS on LTCC Interposer.

This paper reports a 3-axis fully integrated differential capacitive tactile sensor surface-mountable on a bus line. The sensor integrates a flip-bonded complementary metal-oxide semiconductor (CMOS) with capacitive sensing circuits on a low temperature cofired ceramic (LTCC) interposer with Au through vias by Au-Au thermo-compression bonding. The CMOS circuit and bonding pads on the sensor backside were electrically connected through Au bumps and the LTCC interposer, and the differential capacitive gap was formed by an Au sealing frame. A diaphragm for sensing 3-axis force was formed in the CMOS substrate. The dimensions of the completed sensor are 2.5 mm in width, 2.5 mm in length, and 0.66 mm in thickness. The fabricated sensor output coded 3-axis capacitive sensing data according to applied 3-axis force by three-dimensional (3D)-printed pins. The measured sensitivity was as high as over 34 Count/mN for normal force and 14 to 15 Count/mN for shear force with small noise, which corresponds to less than 1 mN. The hysteresis and the average cross-sensitivity were also found to be less than 2% full scale and 11%, respectively.

Solid-State Microjoining Mechanisms of Wire Bonding and Flip Chip Bonding

Low-temperature microjoining, such as wire (or ribbon) bonding, tape automated bonding (TAB), and flip chip bonding (FCB), is necessary for electronics packaging. Each type of microjoining takes on various aspects but has common bonding mechanisms regarding friction slip, plastic deformation, and friction heating. In the present paper, solid-state microjoining mechanisms in Au wire (ball) bonding, FCB, Al wire bonding (WB), and Al ribbon bonding are discussed to systematically understand the common bonding mechanisms. Ultrasonic vibration enhances friction slip and plastic deformation, making it possible to rapidly obtain dry interconnects. Metallic adhesion at the central area of the bonding interface is mainly produced by the friction slip. On the other hand, the folding of the lateral side surfaces of the Au bump, Au ball, and Al wire is very important for increasing the bonded area. The central and peripheral adhesions are achieved by a slip-and-fold mechanism. The solid-state microjoining mechanisms of WB and FCB are discussed based on experimental results.

Fabrication of bottom-emitting organic light-emitting diode panels interconnected with encapsulation substrate by Au[sbnd]Au flip-chip bonding and capillary-driven filling process

We present fabrication and testing of bottom-emitting organic light-emitting diode (OLED) panels based on flip-chip assembly and non-destructive scanning. In this method, the OLED and electric circuits are fabricated on separate substrates and interconnected by low temperature assembly to create a high-performance bottom-emitting OLED including other functions such as thin-film transistor (TFT) circuits. The low temperature assembly process consists of two steps. First, an OLED substrate and encapsulation glass with circuits are bonded at 100°C via AuAu bond. Encapsulation glass is utilized for the functional substrate with circuits. Next, the bonded panel is sealed by capillary underfill within and by applying and curing seal materials to the panel edge. The fabricated OLED was non-destructively evaluated by scanning acoustic microscopy (SAM). The SAM image shows all φ500μm Au bumps were bonded to Au pads, indicating that OLED and encapsulation substrates were assembled. Electroluminescence of the OLED was demonstrated by applying voltage. Stable current-luminance characteristics were obtained for the fabricated OLED with an operating voltage of 3.25V. The results indicate that the proposed fabrication is available for bottom-emitting OLED controlled by TFT circuits. In future, the assembly process can be widely applied to other flexible organic electronic devices with roll assembly by altering OLED or circuits with other devices because this is a simple pressure method with low temperature, achieving encapsulation at same time.

Interconnection reliability and interfacial structure between Au alloy bump and Al pad using ultrasonic bonding

Flip chip technology with Au bumps on a substrace has been widely applied to electronic equipment such as smart phones. The purposes of this study are to examine the effect of Al pad thickness on the bondability of flip chip using ultrasonic bonding and to clarify interfacial structures between Au alloy bumps and Al pads by ultrasonic bonding compared before and after a thermal cycle test. Suitable Al thickness for excellent initial Au/Al bonding without chip cracking are 0.8 μm because a thin Al layer could not reduce stress to a chip under an Al pad during the ultrasonic bonding process. Intermetallic compounds between the Au alloy bump and chip after reflows consisted of five Au-Al layers, and a pure Al layer remained. On the other hand, after the temperature cycle test at 218/423 K, intermetallic compounds between the Au alloy bump and chip were changed into two kinds of Au-Al layers, so a pure Al layer did not exist. In addition, if thick intermetallic compound layers existed around the bonding region, bondability deteriorated easily by thermal stress due to a thermal cycle test, therefore the open failure rate was rising when the Au thickness was 1.2 μm.

Flexible substrate technology for millimeter wave wireless power transmission

In this paper, a technology based on thin flexible polyimide substrate (Kapton) to develop antennas for millimeter wave wireless power transmission is presented. Firstly, we characterize the Kapton polyimide (relative permittivity and loss tangent) using a ring resonator method up to V band. A 60 GHz patch antenna is designed, fabricated, and measured to validate our technology. Crossed-dipoles array antennas at Kuband and K band for energy harvesting are also designed, fabricated, and measured. Then a prototype of crossed-slot dipole antenna at V band is proposed. Finally, a resistivity characterization of Au bump used in flip-chip packaging is done, which leads us one step further toward aheterogeneous integration on flexible substrate of different components for Wireless Sensor Network nodes.

Al 및 SiN 박막 위에 형성된 TiW Under Bump Metallurgy의 스퍼터링 조건에 따른 Au Bump의 접착력 특성

Al 및 SiN 박막 위에 형성된 TiW Under Bump Metallurgy의 스퍼터링 조건에 따른 Au Bump의 접착력 특성

Development of Hard X-ray and Gamma-ray Detector With Transition Edge Sensor for Nuclear Materials Analysis

We have designed and fabricated a hard X-ray and gamma-ray TES spectrometer for nuclear materials analysis. A superconducting tin (Sn) absorber is coupled to the TES film by using a gold (Au) bump post to improve the thermal contact between the absorber and the TES. To obtain a sufficient detection efficiency at the high energy photons near 100 keV, an 8-pixel array of TES microcalorimeters were developed. In this new device, the epoxy glue which is used to connect the absorber and the gold bump post was well controlled and hence the slow component of the decay time constant was improved from 7.82 ms to 4.46 ms compared to our old device. The energy resolution was 131 eV FWHM at 59.5 keV gamma rays, which is better than the limit of HPGe detectors (400 eV FWHM at 60 keV).

Intermetallic Compound Formation and Mechanical Property of Inner Lead Bonding Joints

A Sn-plated Cu lead is bonded with an Au bump to form an inner lead bonding (ILB) joint, and the adhesion strength of the joint is examined using peeling test. Effects of bonding temperature (force) on the joint's adhesion are investigated. The 200-nm-thick Sn layer at the bottom of the Cu lead is consumed, and two reaction product layers are formed at the Cu/Au interface after bonding. One is the ζ-(Au,Cu)5 Sn phase next to Cu, and the other is the α phase, that is, the (Au) or (Cu) solid solution dissolved with minor Sn, next to Au. Nanocracks are easily formed in the α phase layer after peeling test, indicating that the α phase was the mechanically weakest point in the ILB joint. In the ILB joints fabricated at lower bonding temperatures (forces), nanocracks are initiated by peeling test and propagate along the bonding interface, resulting in complete detachment of the Cu lead from the Au bump. Raising the bonding temperatures (forces) contributed to a better coverage of Sn on both sides of the Cu lead and deeper embedment of the Cu lead in the Au bump. The adhesion strength of the ILB joint is enhanced, and accordingly the joint withstands the peeling test without delamination.

Formation of a Metastable Phase at the Interface Between Sn and Ag–Pd Substrates During Liquid-State Reaction

Ag–Pd alloys are widely used as thick-film conductors and are potential alternatives to the expensive Au bump. In this work, because Sn is the primary element in solders, we investigated Sn/Ag–Pd interfacial reactions at 250°C as a means of assessing the reliability and evaluating reflow reactions at joints between solder and Ag–Pd conductor contacts, and in the Ag bump combined with the solder cap. The experimental results showed that Sn/Ag–Pd interfacial reactions at 250°C are different from those of Sn/Ag and Sn/Pd. A metastable Sn–Ag–Pd ternary phase is formed when the amount of Pd added is 20–40 at.%. Because, in commercial applications, at least 20 wt.% Pd (~20 at.% Pd) is used in Ag–Pd alloys to eliminate the silver-migration phenomenon, assessment of the reliability of Ag bumps and the soldered joints of Ag–Pd thick film hybrid circuits must be based on Sn/Ag–Pd interfacial reactions, not those of Sn/Pd and Sn/Ag.

MEMS Wafer‐Level Packaging Technology Using LTCC Wafer

SUMMARYThis paper describes a versatile and reliable wafer‐level hermetic packaging technology using an anodically bondable low‐temperature co‐fired ceramic (LTCC) wafer, in which multilayer electrical feedthroughs can be embedded. The LTCC wafer allows many kinds of microelectromechanical systems (MEMS) to be more flexibly designed and more easily packaged. The hermeticity of vacuum‐sealed cavities was confirmed after 3000 cycles of thermal shock (–40 30 min/+125 30 min) by the diaphragm method. To practically apply the LTCC wafer to a variety of MEMS, the electrical connection between the MEMS on a Si wafer and feedthroughs in the LTCC should be established by a simple and reliable method. We have developed a new electrical connection method: the electrical connection is established by porous Au bumps, which are part of the Au vias exposed in wet‐etched cavities on the LTCC wafer. A 100% yield of both electrical connection and hermetic sealing was demonstrated. A thermal shock test up to 3000 cycles confirmed the reliability of this packaging technology.

Simultaneous fabrication of a through‐glass interconnect via and a bump using dry film resist and submicron gold particles

A process for the simultaneous fabrication of through-glass interconnect vias (TGVs) and gold (Au) bumps using dry film resist and submicron Au particles is proposed. A Ti/Pt/Au layer was sputtered on the top and bottom surfaces of glass vias to improve the adhesion between the glass substrate and submicron Au particles. The submicron Au particles filled the resist holes and glass vias fabricated by photolithography and by the two-electrode method, respectively, and were then sintered. The height and diameter of the fabricated Au bumps were about 20–25 and 200 µm, respectively. The Ti/Pt/Au layer on the surface of the glass substrate was removed by Ar ion milling to isolate each bump electrically. The resistance of a single Au bump and TGV was evaluated using the four-wire ohm method to be about 0.05 Ω. Furthermore, Au bump bonding was demonstrated. Fractured Au bumps and TGVs were observed by scanning electron microscopy after the bonded sample was peeled. It is expected that this fabrication process using a dry film resist and submicron Au particles will be useful in simple packaging processes to form glass interposer substrates or glass integrated circuit chips.