Au Bumps Research Articles

Hybrid Au-Adhesive Bonding Using Planar Adhesive Structure for 3-D LSI

In this paper, we describe a hybrid bonding technology of Au microbump and adhesive using a planar adhesive structure for 3-D large-scale integration (LSI). Hybrid bonding means that both the microbump electrode and adhesive are simultaneously bonded. In 3-D LSI, the gaps between bonded chips are <;10 μm because the pitch of the microbumps is decreased. Conventionally, adhesive resin is injected into the gaps by means of capillary force. However, the filling of the gaps is insufficient due to surface conditions. To address this challenge, we evaluated hybrid bonding with a planar adhesive structure fabricated by chemical-mechanical polishing. The bonding results showed that connection between the Au bumps and adhesive filling in the 6-μm gap between bonded Si chips was achieved without readily visible void in the range of 6 mm × 6 mm. All 900 bumps were also electrically connected. The shear strength of the bonded sample was 13 MPa. Therefore, we determined that the proposed hybrid bonding technology is highly effective for 3-D LSI with fine-pitch microbumps.

Soldering of non-wettable Al electrode using Au-based solder

In manufacturing three-dimensional SiC power modules, the Al electrode of SiC power devices should be soldered to the substrate. However, the Al electrode is difficult to be bonded by a solder due to the naturally formed aluminum oxide on it. In this paper, we describe an effective approach for soldering the non-wettable Al electrode by fabricating a Au-stud bump in the Al electrode together with a Au-20 wt% Sn or Au-12 wt% Ge solder. The soldering initiated at the Au bump and spreaded on the Al electrode. The soldering featured as reactive wetting, realized by the reaction of liquid Au in the Au-base solder and the Al electrode. The activation energy of the Au-20 wt% Sn soldering the Al electrode was Q = 159 kJ/mol. A continuous Au4Al layer formed at the Au-20 wt% Sn bond interface. The shear strength exceeded 60 MPa, ∼1 order magnitude higher than the required shear strength. For the bond with Au-12 wt% Ge solder on the Al electrode with a Au bump, the liquid Au-12 wt% Ge solder reacted with the solid Al electrode and formed a Au-Ge-Al solid solution after solidification. The shear strength of the Au-12 wt% Ge solder on the Al electrode with a Au bump was beyond 50 MPa. Little electrical characteristics of the SiC-SBD changed after the Al electrode was bonded to a circuit substrate using this technology.

Thermal simulation and analysis of flat surface flip-chip high power light-emitting diodes

Conventional GaN-based flip-chip light-emitting diodes (CFC-LEDs) use Au bumps to contact the LED chip and Si submount, however the contact area is constrained by the number of Au bumps, limiting the heat dissipation performance. This paper presents a flat surface high power GaN-based flip-chip light emitting diode (SFC-LED), which can greatly improve the heat dissipation performance of the device. In order to understand the thermal performance of the SFC-LED thoroughly, a 3-D finite element model (FEM) is developed, and ANSYS is used to simulate the thermal performance. The temperature distributions of the SFC-LED and the CFC-LED are shown in this article, and the junction temperature simulation values of the SFC-LED and the CFC-LED are 112.80 °C and 122.97 °C, respectively. Simulation results prove that the junction temperature of the new structure is 10.17 °C lower than that of the conventional structure. Even if the CFC-LED has 24 Au bumps, the thermal resistance of the new structure is still far less than that of the conventional structure. The SFC-LED has a better thermal property.

Magnetic Self-Assembly of Ultra-Thin Chips to Polymer Foils

A self-assembly process is developed for the placement and alignment of Ultra-Thin Chips (UTCs) to polymer foils. The chips are presented within the working range of a magnetic force field, and subsequently driven to and aligned at a target location. A low-viscosity die attach adhesive layer supports chip mobility during alignment, and is UV-cured after assembly to generate a mechanical bond. An adaptive electrical interconnection scheme compensates the position errors present after assembly. Standard Ni + Au bumps provide sufficient magnetization to generate the required alignment force. Numerical modeling confirms that over a long range magnetic forces operate on a chip and drive it to a target location. Also, an asymmetric bump arrangement supports achieving a unique in-plane orientation. Experimentally, chips with a thickness of 20 μm were successfully trapped and aligned with a repeatability of ±100 μm in x and y-direction, and the best achieved cycle time is below 1.0 s. The cycle time depends considerably on the viscosity of the die attach adhesive. The presence of unique in-plane orientations, depending on the bump arrangement, is demonstrated.

Development of Hard X-Ray and Gamma-Ray Spectrometer Using Superconducting Transition Edge Sensor

Superconducting transition edge sensors (TES) are used for high-resolution X-ray spectroscopy. In our group, we have developed Ir/Au-TESs. We have recently started to develop a high-resolution X-ray and gamma-ray spectrometer using our Ir/Au-TES. In this study, we plan to accelerate the response time of the detector system, thus we have designed a new Sn-absorber coupled TES detector system by improving the thermal contact between the TES and the absorber. A superconducting tin absorber is coupled to an Ir/Au superconducting film with a gold (Au) bump post, instead of an epoxy post, which is used conventionally. The pulse height signal, which we obtained from the Au bump post TES, is more than twice as large as that from the epoxy post system, and the slow component of the decay time constant improved to 8.0 ms from 22.0 ms. The energy resolution of the 59.5 keV photoelectron peak is 280 eV FWHM, which is currently dominated by the mechanical vibration of our pulse-tube refrigerator.

Study on Hybrid Au&amp;#x2013;Underfill Resin Bonding Method With Lock-and-Key Structure for 3-D Integration

This paper describes a hybrid Au-underfill resin bonding method with lock-and-key structure for 3-D integration. In 3-D large scale integration (LSI), the gap between stacked chips becomes narrower because the bump dimension and pitch are smaller than those encountered in 2-D LSI. Therefore, the filling of gaps less than 10 μm using capillary forces often becomes insufficient because of the surface condition. To address this challenge, we study a hybrid bonding method in which the metal-metal and resin-resin bonding are carried out simultaneously with a chip resin applied previously only around the bump. To realize hybrid bonding on the entire chip, we fabricate indent and protrusion structures, which are called lock-and-key structures. The key structure is fabricated by a process that can remove the resin on the bumps by O2 plasma irradiation. The lock structure is fabricated by conventional photolithography and dry etching. By means of hybrid bonding with the lock-and-key structure, we have achieved the Au bump bonding and the filling of 4-μm gaps between the stacked chips, concurrently. The cross-sectional transmission electron microscopy image of the bonded sample demonstrated that no significant gap exists at both the Au-Au and resin-resin interfaces. In addition, the shear strength of the sample bonded with resin is 10 times higher than that without the resin. The electrical continuity of the Au bump connections after hybrid bonding has also been determined.

Fabrication of Au nanorod and nanogap split-ring structures by reactive-monolayer-assisted thermal nanoimprint lithography involving electrodeposition

Au nanorods and Au nanogap split-ring (SR) structures were fabricated to investigate the ability of wet etching and Ar ion milling processes to remove an underlying Au electrode layer on shapes of electrodeposited Au structures. A reactive-monolayer-assisted thermal nanoimprint lithography process involving Au electrodeposition was used to make 100 nm × 500 nm Au nanorods and Au nanogap SR structures with widths of 125 nm and two 20 nm gaps. Individual Au bump structures were successfully demonstrated on transparent silica substrates by Ar ion milling and subsequent Cr wet etching. Au nanorod and nanogap SR structures were obtained almost uniformly over a 100-μm square area, which was sufficient to investigate their optical properties. The array comprising electrodeposited Au nanorods showed an anisotropic absorption band, attributable to a transverse plasmon band at wavelengths ranging from 500 to 700 nm when an incident light was linearly polarized perpendicular to the long axis of Au nanorods.

Reliability of chip on glass module fabricated with direct printing method

To investigate the effect of the sintering temperature on the electrical properties of a chip on glass (COG) module, a screen-printed conductive circuit was sintered at various temperatures, viz. 150, 200, 250 and 300^oC for 30min. An anisotropic conductive film (ACF) is a suitable bonding material for the interconnection between a device and printed circuit, because of the conductive particles within it. We expected that the conductive particles in the ACF would provide a good electrical connection and reliability in our study. The electrical properties of the printed Ag circuits improved with increasing sintering temperature. The conductive particles in the ACF were well deformed in between the Au bumps and printed Ag pads after the bonding process. The resistances of the interconnections drastically decreased with increasing sintering temperature. Also, the temperature-humidity reliability of the ACF was investigated by measuring the resistance after the temperature-humidity test (THT) at 85^oC and 85% relative humidity. After the THT, the resistance shows a tendency to decrease when sintered below 200^oC, whereas it increases when sintered over 250^oC. The increase in the resistance due to the effect of surface oxidation is negligible.

Effect of Sintering Temperature on Electrical Properties of Chip on Glass Module with Direct Printing Method

In order to apply the direct printing method to the fabrication of chip on glass (COG) modules, we examined that the effect of the sintering temperature on the electrical properties of a COG module with direct printing method. Firstly, we fabricated an Ag conductive circuit on a glass substrate by the screen-printing method. To investigate its the effect on the electrical properties of the circuit, it was sintered at various temperatures, such as 150, 200, 250, and 300 °C for 30 min. Subsequently, we conducted Au electro-plating for the fabrication of a Si dummy chip. Finally, the flip-chip bonding process was conducted using anisotropic conductive film (ACF). The printed Ag circuits were well formed on the quartz substrate without any shorts or remarkable changes compared with the initial design. The electrical properties of the printed Ag circuits improved with increasing sintering temperature. The conductive particles in the ACF were well deformed in between the Au bumps and printed Ag pads after the bonding process. The four-point probe method was employed to measure the connection resistance of the joints constructed with the Au bumps on the Si chip and printed Ag circuit on the quartz substrate. The resistances of the interconnections drastically decreased with increasing sintering temperature, i.e., subsequently converged from 11.8 Ω to 7.36 mΩ.

Microelectromechanical systems–based visible-near infrared Fabry-Perot tunable filters using quartz substrate

There is a need to develop miniature optical tunable filters for small hyperspectral imagers. We plan to develop a number of miniature Fabry-Perot tunable filters (FPTFs) using microelectromechanical systems (MEMS) technology, each operating over a different wavelength region, to cover spectral regions from the visible to the longwave infrared (IR). Use of a MEMS-based FPTF as a dispersive element will reduce the size, weight, and power requirements of hyperspectral imagers and make them less expensive. A key requirement for such a filter is a large optical aperture. Recently, we succeeded in fabricating FPTFs with a 6 mm optical aperture operating in the visible to near IR spectral region (400 to 800 nm) using commercially available thin quartz wafers as the substrate. The FPTF design contains one fixed silver (Ag) mirror and one electrostatically movable Ag mirror, each grown on a quartz substrate with a low total thickness variation. Gold (Au) bumps are used to control the initial air gap distance between the two mirrors, and Au-Au bonding is used to bond the device. We describe material selection, device design, modeling, fabrication, interferometric, and spectral characterizations.

Spectral imaging characterization of quartz MOEM tunable Fabry-Perot filter

Recently, prototype MOEM tunable Fabry-Perot filters operating from 400 to 800 nm were fabricated under a program to design miniature hyperspectral imagers operating from the visible to the longwave infrared. The filter design uses two semitransparent 30 nm thick silver-film mirrors, one fixed and the other moving, on a low-cost thin commercial quartz substrate. The moving mirror is supported by three leaf spring arms, which are fabricated by wet etching of the quartz substrate. The tuning of the transmitted wavelength of light from the filter is achieved by electrostatically actuating the moving mirror to vary the distance between the two mirrors. The size of the device is 18×24 mm2. The fixed part has a 6 mm diameter mirror and three electrodes to apply voltages, and the moving mirror is used as a ground electrode. Au bumps deposited on both parts control the initial air gap distance, and an Au-Au bonding is used to bond the two parts together. The spectral imaging performance of the MOEM filter is characterized using a spectrally tunable source and a CCD camera with suitable optics. The authors present a brief description of the filter, its characteristics, spectral imaging characterization experiment and results.

Room-Temperature Microjoining of LSI Chips on Poly(ethylene naphthalate) Film Using Mechanical Caulking of Au Cone Bump

We show that room-temperature bonding of LSI chips on a resin film made of poly(ethylene naphthalate) (PEN) can be realized by using mechanical caulking of a cone-shaped bump electrode made of Au. A 20-µm-pitch area array of cone-shaped Au bumps was fabricated on a Si wafer by photolithography and electroplating. The counter electrode with cross-shaped slits on the PEN film was composed of a Au (top)/Ni/Al (bottom) layered structure, where Ni and Au layers were deposited by electroless plating on patterned Al. Bonding of about 10,000 bump connections with 184 mΩ/bump has been achieved at room temperature.

Electrical interconnection in anodic bonding of silicon wafer to LTCC wafer using highly compliant porous bumps made from submicron gold particles

An anodically bondable low temperature cofired ceramic (LTCC) wafer offers a versatile, clean and reliable wafer-level hermetic packaging for MEMS. This paper reports electrical interconnection in parallel with anodic bonding between MEMS on a Si wafer and vias in the LTCC wafer using porous Au bump. The Au bump is made of submicron Au particles, and so compliant as it easily absorbs large height difference. The LTCC wafer with the Au bumps and an SOI wafer with Au/Pt/Cr pads and diaphragms were anodically bonded. 100% yield of both electrical interconnection and hermetic sealing was demonstrated. Heat cycle test confirmed the reliability of both electrical interconnection and hermeticity. In addition, the transfer of the porous Au bumps from a mother glass wafer to a target LTCC wafer was demonstrated.

Thinner and Miniaturization Embedded Device Package, MCeP, for PoP and Module Application

Along with miniaturization and high functionality of electronics, many embedded device substrates and packages have been developed by various companies. We have been also developing embedded device package named MCeP, Molded Core embedded Package. This package consists of base substrate, upper substrate and molding resin. These substrates material is conventional organic base. Bare IC devices without re-routing are mounted on inner surface of base substrate. Upper substrate and base substrate are connected electrically by copper core solder balls. The space between upper and base substrate is encapsulated by molding resin. MCeP is possible to be adopted for bottom package alternative of PoP. For thinner PoP application less than 1.0mm height, thinner MCeP less than 300um has been investigated. Base substrate has 3 conductive layers and thickness is 130um. Upper substrate has 2 conductive layers and thickness is 95um. Embedded layer thickness is 52.5um. For original MCeP, IC device is mounted by flip chip bonding using Au bump and tin-silver solder interconnection. The space between IC device and base substrate is encapsulated by under-filling resin. It is necessary to keep under-filling resin flow area around IC device. Because of this resin flow area, package size should be enlarged. To miniaturize package size, solder bumped IC device and encapsulation by molding resin instead of under-filling resin were used, then resin flow area was eliminated. MCeP is possible to use bottom package alternative for PoP and module application with IC device and passive components embedded.

MEMS Wafer-level Packaging Technology Using LTCC Wafer

SUMMARY This paper describes a versatile and reliable wafer-level hermetic packaging technology using an anodically bondable low-temperature co-fired ceramic (LTCC) wafer, in which multilayer electrical feedthroughs can be embedded. The LTCC wafer allows many kinds of microelectromechanical systems (MEMS) to be more flexibly designed and more easily packaged. The hermeticity of vacuum-sealed cavities was confirmed after 3000 cycles of thermal shock (–40 30 min/+125 30 min) by the diaphragm method. To practically apply the LTCC wafer to a variety of MEMS, the electrical connection between the MEMS on a Si wafer and feedthroughs in the LTCC should be established by a simple and reliable method. We have developed a new electrical connection method: the electrical connection is established by porous Au bumps, which are part of the Au vias exposed in wet-etched cavities on the LTCC wafer. A 100% yield of both electrical connection and hermetic sealing was demonstrated. A thermal shock test up to 3000 cycles confirmed the reliability of this packaging technology.

Effects of ultrasonic bonding parameters on reliability of flip chip GaN-based light emitting diode

This work applied the ultrasonic bonding to package flip chip GaN-based light emitting diodes (flip chip LEDs) on Si substrates. The effects of ultrasonic bonding parameters on the reliability of flip chip GaN-based LED were investigated. In the sequent aging tests, samples were driven with a constant current of 80 mA for hundreds hours at the room temperature. It was found that the electroluminescence (EL) intensity variation had a large correlation to the ultrasonic power, and then to the bonding temperature and force. A high bonding temperature and ultrasonic power and a proper bonding force improved the EL intensity significantly. It was contributed to a strong atom inter-diffusion forming a stable joint at the bonding interface. The temperature fluctuation in the aging test was the main factor to generate a high inner stress forming delamination at the interface between the chip and Au bump. As a result, delamination had retarded the photons to emit out of the LED packaging and decay its EL intensity.

Ultra-fine pitch chip-on-glass (COG) bonding with metal bumps having insulating layer in the side walls using anisotropic conductive film (ACF)

We developed a new ultra-fine pitch chip-on-glass (COG) bonding technique using insulated metal bumps and anisotropic conductive film (ACF). An insulating layer was formed by spin coating a photosensitive insulating polymer and subsequently exposing it without any mask. The shape of the insulating layer coverage on the side walls of the metal bumps can be controlled by changing the exposure time and the viscosity of the photosensitive insulating polymer. In our experiment, we successfully fabricated COG joints with a 25 μm pitch using Au bumps with an insulating layer on their side walls and a conventional single-layer ACF. When the bumps were covered with the photosensitive insulating polymer, a few conductive particles were trapped between neighboring bumps and many conductive particles were embedded between bumps and pads. The electrical resistance between neighboring bumps was measured by the two-point probe method. The resistances were measured only in uncoated specimens. The measured resistance indicates that electrical shorting between neighboring bumps occurred in uncoated specimens. Therefore, electrical shorting was successfully prevented by the insulating layer on the side walls of the bumps.

Microjoining of LSI Chips on Poly(ethylene naphthalate) Using Compliant Bump

We show that microjoining of LSI chips on a film made of poly(ethylene naphthalate) (PEN), whose glass transition temperature is 155 °C, can be realized by using a cone-shaped compliant bump for flexible electronics. A 20-µm-pitch area array of cone-shaped Au bumps was fabricated on a Si wafer by photolithography and electroplating. The counter electrode on the PEN film was composed of a Au (top)/Ni/Al (bottom) layered structure, where Ni and Au layers were deposited by electroless plating on patterned Al. The bonding was carried out at 150 °C. More than 10,000 connections with 108 mΩ/bump were achieved. Mechanical analysis using finite element method indicates that the joining is due to deformation of the cone-shaped Au bumps.

Surface activated bonding of copper through silicon vias and gold stud bumps at room temperature

A comprehensive investigation of the surfaces of copper through silicon vias (Cu-TSVs) and gold stud bumps is presented. These vias and stud bumps were bonded at room temperature using a nanobonding and interconnection equipment. The influence of heating on the bonded interface was also studied. In order to achieve an intimate contact between the Au-stud bumps and Cu-TSVs, the stud bumps were flattened under an external force of 20 N before bonding. The surface roughness of the flattened area was improved due to deformation of the bumps. Specimens with high deformation provided better alignment accuracy than those with low deformation. The Cu-TSV surface showed inhomogeneous behavior due to the influence of electroplating and chemical mechanical polishing. Tensile pulling test of the bonded interfaces showed three fractures modes in the bulk of the Au bump and the Au pad. The electrical resistance of the bonded interface was dependent on the surface morphology of the bumps and TSVs, the distance between the bumps and TSVs, the locations of the bumps and TSV with respect to the argon fast atom beams, and the distribution of external force during bonding. Heating at 200 °C for 60 h in air increased the electrical resistance of the bonded interface. This investigation shows that the vertical integration of Au/Cu at room temperature and low bonding force can be applied to three-dimensional interconnections for low cost miniaturized systems.

Wafer Level Integration of MMIC and Microwave IPD with Metal/BCB Multilayer Interconnection Based on Low Resistance Silicon

A new high-density wafer-level integration of a GaAs based monolithic microwave integrated circuit (MMIC) chip and a microwave integrated passive device (IPD) is presented. This integration technology, an important and IC-compatible option for system-in-package (SiP), utilizes bulk Si fabrication and film deposition based multichip module (MCM-D) process. MMIC is entirely embedded into the silicon wafer while IPDs are integrated on the dielectric layers simultaneously with the metal/BCB multilayer interconnection. Key fabrication processes and crucial technologies are described in detail. Normal silicon wafer is selected as substrate because of its mature processing technology, low cost, good thermal dissipation as well as its thermal expansion matching with GaAs. To obtain excellent microwave performances and good planarization, thick photosensitive BCB of 25um/layer is adopted as dielectric and thus the use of tapered via that is hollow inside or filled by BCB is a cost-effective way to accomplish inter-layer connection instead of Au bump bonding or column used in dry-etch BCB process. Further promotions on microwave performances are achieved by the shielding effect through ground layer coverage on silicon surface and the application of microstrip lines. Several experiment results such as dc inter-layer connection resistance and thermal resistance measurements are complemented to investigate the characteristic of the whole package. The Microwave properties of the integration sample are measured by transmission performance test from 15GHz to 30GHz. The measurement results are analyzed and discussed comparing with the theoretical or simulation results.