ATLAS-3D Device Simulator Research Articles

TCAD RF Performance Investigation of V-Shaped Groove Gate MOSFET

For the first time, the RF performance analysis of a V-shaped grooved (V-GG) Gate MOSFET has been presented and compared with the trapezoidal groove gate (TGG) and rectangular groove gate (RGG) MOSFETs, using ATLAS-3D device simulator, for future wireless and ULSI applications. The study reveals that V-GG MOSFET exhibits significantly enhanced performance as compared to its conventional counterparts in terms of the figure of merits (FOM): drain current, transconductance (gm), cut-off frequency (ft), maximum transducer power gain, stern stability factor (K), and, S-parameters.

A novel bottom-spacer ground-plane (BSGP) FinFET for improved logic and analog/RF performance

FinFET for system-on-chip (SoC) applications like logic/SRAM need shorter fins, whereas in analog/RF and global interconnect drivers need taller and multi-fins. To tackle this issue, we are proposing a novel bottom-spacer ground-plane (BSGP) FinFET structure. The BS helps in increasing the source-channel barrier potential by increasing BS height (BSH). The GP attributes to reducing the drain-induced barrier lowering (DIBL) and subthreshold swing (S) by grounding the source and drain electric filed owing to better gate control over the channel region. The essential process flow required for creating the BSGP FinFET structure is presented in this paper. The short-channel parameters such as ON-state current to OFF-state current (ION/IOFF) ratio, DIBL, and S are evaluated, analyzed, and compared with standard FinFET using ATLAS 3D Device simulator. In addition to that, some of the analog/RF performance metrics such as transconductance (gm), Output conductance (gd), transconductance generation factor (TGF), early voltage (VEA), intrinsic gain (AV), cut-off frequency (fT), gain transconductance frequency product (GTFP), gain frequency product (GFP) and transconductance frequency product (TFP) are extracted and compared at different BSH (=30, 40, 50 nm). It has been noticed that the proposed device is best suitable for SoC applications and future technological nodes.

Reliability of Sub-20 nm Black Phosphorus Trench (BP-T) MOSFET in High-Temperature Harsh Environment

In this work, the high-temperature reliability of the Black Phosphorus Trench (BP-T) MOSFET device has been analyzed. When the temperature is very high (500 K), the proposed device (BP-T-MOSFET) shows very high reliability with less effects in the device performance. The device is also calibrated with the experimental data. All the simulation has been performed using ATLAS-3D device simulator. BP-T-MOSFET shows high-temperature reliability in terms of reduced sub-threshold current, hot-electron injection gate current, and impact ionization substrate current. Further, higher switching ratio (Ion/Ioff), electron mobility, and electron velocity have also been observed owing to the electrical properties of black phosphorus used in the trench gate which shows the potential in a high-temperature environment. Owing to trench structure and electrical properties of black phosphorus, BP-T-MOSFET has significant device efficiency and low leakage currents at high temperatures which prove as highly shrieked MOS device applications in harsh temperature environment.

Modeling and Simulation of Junctionless Double Gate Radiation Sensitive FET (RADFET) Dosimeter

A junctionless double gate radiation sensitive FET (RADFET) has been proposed to improve the radiation sensitivity and its application as CMOS-based dosimeter is discussed. Analytical model has been developed from 2D Poisson equation using variable separation technique and electrical performance of the proposed architecture has been compared with the conventional double gate (DG) RADFET. The comparison of device characteristics shows that the JL DG RADFET exhibits better electrical performance and sensitivity as compare to conventional DG RADFET. The model is verified using ATLAS 3D device simulation software.

Cylindrical gate all around Schottky barrier MOSFET with insulated shallow extensions at source/drain for removal of ambipolarity: a novel approach

In this paper TCAD-based simulation of a novel insulated shallow extension (ISE) cylindrical gate all around (CGAA) Schottky barrier (SB) MOSFET has been reported, to eliminate the suicidal ambipolar behavior (bias-dependent OFF state leakage current) of conventional SB-CGAA MOSFET by blocking the metal-induced gap states as well as unwanted charge sharing between source/channel and drain/channel regions. This novel structure offers low barrier height at the source and offers high ON-state current. The ION/IOFF of ISE-CGAA-SB-MOSFET increases by 1177 times and offers steeper subthreshold slope (~60 mV/decade). However a little reduction in peak cut off frequency is observed and to further improve the cut-off frequency dual metal gate architecture has been employed and a comparative assessment of single metal gate, dual metal gate, single metal gate with ISE, and dual metal gate with ISE has been presented. The improved performance of Schottky barrier CGAA MOSFET by the incorporation of ISE makes it an attractive candidate for CMOS digital circuit design. The numerical simulation is performed using the ATLAS-3D device simulator.

Analytical drain current model for Gate and Channel Engineered RingFET (GCE-RingFET)

In this work, an analytical drain current model for Gate and Channel Engineered RingFET (GCE-RingFET) has been developed by solving 2D-Poisson equation in cylindrical coordinates. The authenticity of proposed model for GCE-RingFET architecture has been justified by comparing the analytical results with simulation results obtained using ATLAS 3D device simulation. Performance comparison of GCE-RingFET with the conventional RingFET device architectures has been performed. Various important performance metrics such as surface potential, transfer characteristic (Ids-Vgs), ION/IOFF ratio, Threshold voltage roll off, Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL), Trans-conductance Generation Efficiency (gm/Ids), have been investigated.

Analytical modeling simulation and characterization of short channel Junctionless Accumulation Mode Surrounding Gate (JLAMSG) MOSFET for improved analog/RF performance

An analytical model for Junctionless Accumulation Mode Surrounding Gate (JLAMSG) MOSFET is developed using superposition technique. The model incorporates source/drain and channel depletion for an accurate analysis. The device parameter dependent electrostatic center potential, drain current (IDS) and subthreshold slope (SS) have been evaluated. The numerical simulation results using ATLAS-3D device simulator are in good agreement with the results obtained from the developed analytical model. A comparative assessment between Junctionless (JL) and Junctionless Accumulation Mode (JLAM) Surrounding Gate (SG) devices for analog/RF performance is also carried out. The superiority of JLAMSG MOSFET over Junctionless Surrounding Gate (JLSG) is discussed for Analog and RF application.

Analytical model of threshold voltage degradation due to localized charges in gate material engineered Schottky barrier cylindrical GAA MOSFETs

The threshold voltage degradation due to the hot carrier induced localized charges (LC) is a major reliability concern for nanoscale Schottky barrier (SB) cylindrical gate all around (GAA) metal–oxide–semiconductor field-effect transistors (MOSFETs). The degradation physics of gate material engineered (GME)-SB-GAA MOSFETs due to LC is still unexplored. An explicit threshold voltage degradation model for GME-SB-GAA-MOSFETs with the incorporation of localized charges (Nit) is developed. To accurately model the threshold voltage the minimum channel carrier density has been taken into account. The model renders how +/− LC affects the device subthreshold performance. One-dimensional (1D) Poisson’s and 2D Laplace equations have been solved for two different regions (fresh and damaged) with two different gate metal work-functions. LCs are considered at the drain side with low gate metal work-function as Nit is more vulnerable towards the drain. For the reduction of carrier mobility degradation, a lightly doped channel has been considered. The proposed model also includes the effect of barrier height lowering at the metal–semiconductor interface. The developed model results have been verified using numerical simulation data obtained by the ATLAS-3D device simulator and excellent agreement is observed between analytical and simulation results.

TCAD RF performance investigation of Transparent Gate Recessed Channel MOSFET

In this paper, analog/RF performance and small signal behavior of Transparent Gate Recessed Channel (TGRC) MOSFET has been investigated in terms of transconductance, DIBL, channel resistance parasitic capacitances, cut-off frequency and maximum oscillator frequency. Results so obtained are compared with Conventional Recessed Channel (CRC) MOSFET at THz frequency range, using ATLAS-3D device simulator. Furthermore, the impact of technology parameter variations in terms of gate length (Lg) has also been evaluated. Result shows that there is 42% enhancement in cut-off frequency, 132% increment in maximum oscillator frequency and significant improvement in parasitic capacitances for TGRC-MOSFET due to reduced short channel effects (SCEs) and enhanced on-current driving capabilities thus, reflecting its significance in high-frequency THz range applications.

Nanoscale T-shaped Double Gate DG MOSFET: Numerical Investigation for Analog/RF and Digital Performance

The present work demonstrates the investigation of T-shaped Double Gate MOSFET for analog and digital performance. The 2D analytical modeling scheme is presented using Evanescent Mode Analysis (EMA). The applicability of the proposed model has been verified using ATLAS 3D device simulation. The device exploits peaks in the electric field inside the channel (due to T-shaped gate) for better carrier transport efficiency and subsequently higher drain current and trans-conductance. The impact of dielectric constant of the void layer (due to T-shaped gate) on the electrostatic of the device has been investigated using basic electrical parameters such as: sub-threshold slope, Drain Induced Barrier Lowering DIBL, device gain and Ion/Ioff ratio. The comparative study between T-shaped DG with the conventional DG MOSFET is also presented.

Modeling and simulation of Double Gate Junctionless Transistor considering fringing field effects

In the present work, the performance of DG-JL transistor has been analysed using analytical modeling scheme as well as 3D device simulation technique. Thus an advance two dimensional analytical sub-threshold drain current model for Double Gate Junctionless (DG-JL) Transistor is presented in this work by considering the impact of fringing field from the gate to source/drain region using conformal mapping technique. The results obtained from proposed model have been verified with the ATLAS 3D device simulation software results. The relevant Short Channel Effect parameters like threshold voltage roll off, Drain Induced Barrier Lowering (DIBL) and Subthreshold Slope (S) are also evaluated using modeling scheme. In addition to this, the suitability of DG-JL Transistor for low voltage digital and analog applications has been investigated through exhaustive device simulation using ATLAS 3D device simulation software only. In essence, this work provides the dependencies of the device performance on the physical device parameters of DG-JL transistor for its assessment for better digital and analog operation.

Temperature Dependent Sub threshold Drain Current Model for Junction less Gate all Around MOSFET with High-K Gate Stack

A temperature dependent sub threshold drain current model for junction less (JL) Gate all around (GAA) MOSFET with high-k Gate Stack is developed in this paper. Poisson’s equation in cylindrical coordinate has been solved using Parabolic Potential Approximation (PPA). The effect of temperature variation from 300-500 K on the sub threshold performance of the JL-GAA MOSFET by varying the gate stack thickness has been obtained using the proposed model. The developed model has also been used to study the Sub threshold- Slop of JL-GAA MOSFET at high ambient temperature. Band-gapnarrowing is also included in the analytical model as the doping concentration is very high. Atlas-3D device simulation tool has been used for the numerical simulations. Developed temperature dependent model for JL-GAA MOSFET with high-k dielectric has close agreement with the simulation results. Developed model is very useful for the device optimization; as the device dimensions reduces in radial direction the oxide thickness reduction becomes necessary and the use of high-k stack as a dielectric is demanded.

Impact of gate material engineering(GME) on analog/RF performance of nanowire Schottky-barrier gate all around (GAA) MOSFET for low power wireless applications: 3D T-CAD simulation

In this paper Gate Material Engineered (GME) Gate-Stack (GS) silicon nanowire Schottky-Barrier (SB) Gate All Around (GAA) MOSFET and Single Material Gate Stack Schottky-Barrier Source/Drain Gate All Around (SM-GS-SB-S/D GAA) structures are proposed for low- power wireless applications. The Analog/RF performance for wireless applications of these devices are demonstrated. The effect of Schottky-Barrier (Metal) S/D is studied for Single Metal (SM)–SB-GAA, (Dual Metal) DM-SB-GAA, SM-GS-SB-GAA and GME-GS-SB-GAA MOSFETs, and it is found that GME-GS-SB-GAA MOSFET with metal drain source shows much improved performance in terms of transconductance (gm), output conductance (gd), Early Voltage (VEA), Maximum Transducer Power Gain, cut-off frequency (fT), and Ion/Ioff ratio. Further, harmonic distortion for wireless applications is also studied using ATLAS-3D device simulator. Due to low parasitic S/D resistance the metal Source/Drain DM-GS-SB-S/D-GAA MOSFET demonstrates remarkable Ion of~31.8μA/μm and saturation transconductance gm of~68.2μS with improved third order derivative of transconductance gm3.

A new T-Shaped Source/Drain Extension (T-SSDE) Gate Underlap GAA MOSFET with enhanced subthreshold analog/RF performance for low power applications

In the proposed work, a novel T-Shaped Source/Drain Extension (T-SSDE) Gate Underlap Gate All Around (GAA) MOSFET is presented and its performance is compared with that of corresponding Conventional Gate Underlap GAA MOSFET using ATLAS-3D device simulator. A quantitative study of main figure of merits (FOMs) for T-SSDE Underlap GAA has been carried out at different Gate Underlap lengths. It is shown that in T-SSDE, short channel effects (SCEs) are suppressed due to enhanced carrier transport efficiency. The results show an improvement in drain current, Ion/Ioff ratio, transconductance, high unity-gain frequency fT and superior analog/RF performance as compared to conventional Gate Underlap GAA MOSFET, thus, making it a better substitute of conventional Underlap Gate GAA devices for faster switching and low power applications.

Comparative Study of Silicon-on-Nothing and III–V-on-Nothing Architecture for High Speed and Low Power Analog and RF/Digital Applications

This paper investigates the impact of channel material engineering on the performance of silicon-on-nothing (SON) architecture for 32-nm technology node. The analog performance of SON architecture in terms of drive current Ids, transconductance (gm), early voltage Vea, trans-conductance generation efficiency gm/Ids, and output resistance Rout with different channel material, i.e., Si, SiGe, Ge, GaAs, and InP has been investigated by using ATLAS 3D device simulation. The impact of temperature variation on the analog performance of the device has also been studied. Due to high mobility channel material (i.e., for III-V-based MOSFET), device shows excellent performance for microwave application because of its high current gain (h21), unilateral power gain, and maximum available power gain Gma. Furthermore, the impact of high mobility channel material on the digital performance of the device has also been investigated by monitoring the CMOS inverter characteristics, i.e., voltage transfer characteristics and noise margin.

Scattering parameter based modeling and simulation of symmetric tied-gate InAlAs/InGaAs DG-HEMT for millimeter-wave applications

This paper analyses the RF performance of the symmetric tied-gate In 0.52Al 0.48As/In 0.53Ga 0.47As DG-HEMT in terms of its maximum frequency of oscillation ( f max) and the other important figures of merit that include Maximum Unilateral Transducer Power Gain and the Maximum Stable Gain. This comprehensive investigation has been done on the basis of scattering parameters in order to judge the potential of InAlAs/InGaAs DG-HEMT as the device for future millimeter wave frequency applications. The effect of parasitic elements has also been included in the analytical model which leads to better correspondence with the experimental results. The analytical results thus obtained using the charge control model are compared and found to agree well with both the ATLAS-3D device simulation results as well as the experimental results.

Two-dimensional analytical subthreshold model of graded channel DG FD SOI n-MOSFET with gate misalignment effect

A two-dimensional (2-D) analytical subthreshold model is developed for a graded channel double gate (DG) fully depleted SOI n-MOSFET incorporating a gate misalignment effect. The conformal mapping transformation (CMT) approach has been used to provide an accurate prediction of the surface potential, electric field, threshold voltage and subthreshold behavior of the device, considering the gate misalignment effect to be on both source and drain side. The model is applied to both uniformly doped (UD) and graded channel (GC) DG MOSFETs. The results of an analytical model agree well with 3-D simulated data obtained by ATLAS-3D device simulation software.