Abstract
In this work, an analytical drain current model for Gate and Channel Engineered RingFET (GCE-RingFET) has been developed by solving 2D-Poisson equation in cylindrical coordinates. The authenticity of proposed model for GCE-RingFET architecture has been justified by comparing the analytical results with simulation results obtained using ATLAS 3D device simulation. Performance comparison of GCE-RingFET with the conventional RingFET device architectures has been performed. Various important performance metrics such as surface potential, transfer characteristic (Ids-Vgs), ION/IOFF ratio, Threshold voltage roll off, Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL), Trans-conductance Generation Efficiency (gm/Ids), have been investigated.
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