Asynchronous Sequential Circuits Research Articles

비-기본 모드 고장이 존재하는 비동기 순차 회로에 대한 모델 정합 제어

This paper proposes a novel corrective controller that achieves model matching for asynchronous sequential circuits vulnerable to faults occurring to transient states. When such faults occur, asynchronous sequential circuits, in the course of exhibiting their transient behaviors, experience unauthorized state transitions, thereby reaching faulty next stable states. We will address the existence condition and the design procedure for a proper corrective controller that matches the stable-state behavior of the controlled asynchronous sequential circuit to that of a reference model while eliminating the adverse effects of all faults occurring in transient states. The corrective controller and the asynchronous sequential circuit will be implemented on a field-programmable gate array (FPGA) to evaluate the efficiency and applicability of the proposed control scheme.

Evaluation of Clause-Column Table method to design of MIC hazard-free in asynchronous finite state machines

Asynchronous finite state machines are of great interest because they use fewer transistors to manufacture them. However, find the minimum resources in logic modeling is an NP-Problem, since the search space increase exponentially. Although this problem is studied for some time, there is still space for newer researches. Mostly, in new computational methods to improve performance in solving logical optimization in finite state machines. Thus, this paper presents a study and evaluation of heuristic algorithms for the optimization of asynchronous finite state machines, to obtain the smallest possible circuit. Thus, the Clause-Column Table and Quine-McCluskey algorithms are combined in order to propose an algorithm capable of minimizing asynchronous sequential circuits. Tests and results show that it is possible to synthesize circuits in a reasonable time, but with some logical errors. It may be concluded that it still needs research, even though it is not such a recent line of research.

A Novel Asynchronous CA Neuron Model: Design of Neuron-Like Nonlinear Responses Based on Novel Bifurcation Theory of Asynchronous Sequential Logic Circuit

This paper presents a novel asynchronous sequential logic circuit neuron model, the nonlinear dynamics of which is described by an asynchronous cellular automaton. As a novel theoretical analysis tool for the model, a continuous-discrete hybrid Poincare map is derived. The map reveals that the presented model can reproduce fundamental dynamic properties and typical bifurcation mechanisms of a biologically plausible neuron model. Using the bifurcation analysis results, systematic design methods of the presented model are proposed. It is shown that the design methods enable the presented model to reproduce typical nonlinear response curves of neurons as well as their underlying bifurcation mechanisms. In addition, the model is implemented in a field programmable gate array and experiments validate its operation. It is shown that the presented model can be implemented by fewer circuit elements and consumes lower power compared to typical conventional neuron models.

병렬 결합된 비동기 순차 회로에서의 내고장성 구현

병렬 결합된 비동기 순차 회로에서의 내고장성 구현

Static hazard elimination for a logical circuit using quantum dot cellular automata

Quantum dot cellular automata (QCA) is an upcoming nano-technology for its high speed and low power operation in the field of nano-science and nano-electronics. As QCA overcomes the drawbacks of CMOS technology, it has appreciable applications in quantum computation. There are thousands of designs of different logical circuits using QCA but there is no hazard free design of the logical circuits in the field of QCA. In a circuit, hazards always produce an unpredictable output which can be avoided. In this paper, both hazardous and hazard-free asynchronous sequential circuits are considered and compared in terms of kink energy. It is shown that hazard free asynchronous circuit performs better in terms of kink energy in the field of QCA.

정적 교정 제어기를 이용한 비동기 순차 회로의 내고장성 구현

비동기 순차 회로를 위한 교정 제어기는 회로를 재설계하지 않고도 회로 내에 존재하는 여러 고장을 탐지하고 극복하는 능력을 보인다. 이번 논문에서는 교정 제어기의 크기를 줄이기 위한 방법으로서 정적 교정 제어기(static corrective controller)를 제안한다. 동적 제어기에 비해 정적 제어기는 제어기 상태가 필요 없으므로 조합 회로(combinational circuit)만으로 구현 가능하다. 본 논문에서는 상태 천이 고장에 대한 정적 내고장성 교정 제어기가 존재할 조건과 설계 과정을 규명한다. 또한 제안된 제어 기법을 FPGA로 구현된 SEU 오류 카운터에 적용하여 그 효용성을 실험적으로 검증한다. Corrective controllers enable fault diagnosis and tolerance for various faults in asynchronous sequential circuits without resort to redesign. In this paper, we propose a static corrective controller in order to decrease the size of the controller. Compared with dynamic controllers, static controllers can be made using only combinational circuits, as they need no inner states. We address the existence condition and design procedures for static corrective controllers that overcome state transition faults. To show the validity and advantage, the proposed controller is applied to an SEU error counter implemented on FPGA.

An Asynchronous Recurrent Network of Cellular Automaton-Based Neurons and Its Reproduction of Spiking Neural Network Activities

Modeling and implementation approaches for the reproduction of input-output relationships in biological nervous tissues contribute to the development of engineering and clinical applications. However, because of high nonlinearity, the traditional modeling and implementation approaches encounter difficulties in terms of generalization ability (i.e., performance when reproducing an unknown data set) and computational resources (i.e., computation time and circuit elements). To overcome these difficulties, asynchronous cellular automaton-based neuron (ACAN) models, which are described as special kinds of cellular automata that can be implemented as small asynchronous sequential logic circuits have been proposed. This paper presents a novel type of such ACAN and a theoretical analysis of its excitability. This paper also presents a novel network of such neurons, which can mimic input-output relationships of biological and nonlinear ordinary differential equation model neural networks. Numerical analyses confirm that the presented network has a higher generalization ability than other major modeling and implementation approaches. In addition, Field-Programmable Gate Array-implementations confirm that the presented network requires lower computational resources.

Fuzzy delay model based fault simulator for crosstalk delay fault test generation in asynchronous sequential circuits

In this paper, a fuzzy delay model based crosstalk delay fault simulator is proposed. As design trends move towards nanometer technologies, more number of new parameters affects the delay of the component. Fuzzy delay models are ideal for modelling the uncertainty found in the design and manufacturing steps. The fault simulator based on fuzzy delay detects unstable states, oscillations and non-confluence of settling states in asynchronous sequential circuits. The fuzzy delay model based fault simulator is used to validate the test patterns produced by Elitist Non-dominated sorting Genetic Algorithm (ENGA) based test generator, for detecting crosstalk delay faults in asynchronous sequential circuits. The multi-objective genetic algorithm, ENGA targets two objectives of maximizing fault coverage and minimizing number of transitions. Experimental results are tabulated for SIS benchmark circuits for three gate delay models, namely unit delay model, rise/fall delay model and fuzzy delay model. Experimental results indicate that test validation using fuzzy delay model is more accurate than unit delay model and rise/fall delay model.

Fault Tolerant Control for Spaceborne Dual Ring Counters with Selective Overriding

Among primary asynchronous sequential circuits, ring counters are used as an important building block in various spaceborne digital systems. As they are subject to adverse effects of radiation, it is imperative that they be given fault tolerance mechanism for robust operation. This paper presents a corrective control scheme for tolerating state transition faults in ring counters. The considered ring counter has the structure of Double Modular Redundancy (DMR), in which some selected memory bits of each ring counter module can override the counterpart values of the other module. With this structure, we can design a static corrective controller that tolerates any state transition fault occurring to the dual ring counter. Though the state information is unavailable, we can implement a simple fault tolerant control scheme using corrective control. The proposed control scheme is validated in VHDL experiments.

Asynchronous cellular automaton-based neuron: theoretical analysis and on-FPGA learning.

A generalized asynchronous cellular automaton-based neuron model is a special kind of cellular automaton that is designed to mimic the nonlinear dynamics of neurons. The model can be implemented as an asynchronous sequential logic circuit and its control parameter is the pattern of wires among the circuit elements that is adjustable after implementation in a field-programmable gate array (FPGA) device. In this paper, a novel theoretical analysis method for the model is presented. Using this method, stabilities of neuron-like orbits and occurrence mechanisms of neuron-like bifurcations of the model are clarified theoretically. Also, a novel learning algorithm for the model is presented. An equivalent experiment shows that an FPGA-implemented learning algorithm enables an FPGA-implemented model to automatically reproduce typical nonlinear responses and occurrence mechanisms observed in biological and model neurons.

Simulation-based ATPG for low power testing of crosstalk delay faults in asynchronous circuits

A new multi–objective genetic algorithm has been proposed for testing crosstalk delay faults in asynchronous sequential circuits that reduces average power dissipation during test application. The proposed Elitist Non–dominated Sorting Genetic Algorithm (ENGA)–based Automatic Test Pattern Generation (ATPG) for crosstalk induced delay faults generates test pattern set that has high fault coverage and low switching activity. Redundancy is introduced in ENGA–based ATPG by modifying the fault dropping phase and hence a very good reduction in transition activity is achieved. Tests are generated for several asynchronous SIS benchmark circuits. Experimental results demonstrate that ENGA gives higher fault coverage, reduced transitions and compact test vectors for most of the asynchronous benchmark circuits when compared with those generated by Weighted Sum Genetic Algorithm (WSGA).

총이온화선량에 의한 고장이 존재하는 비동기 순차 회로의 교정 제어

This paper presents a control theoretic approach to realizing fault tolerance in asynchronous sequential circuits. The considered asynchronous circuit is assumed to work in space environment and is subject to faults caused by total ionizing dose (TID) effects. In our setting, TID effects cause permanent changes in state transition characteristics of the asynchronous circuit. Under a certain condition of reachability redundancy, it is possible to design a corrective controller so that the closed-loop system can maintain the normal behavior despite occurrences of TID faults. As a case study, the proposed control scheme is applied to an asynchronous arbiter implemented in FPGA.

A Generalized Rotate-and-Fire Digital Spiking Neuron Model and Its On-FPGA Learning

A generalized rotate-and-fire digital spiking neuron model that can be implemented by a simple asynchronous sequential logic circuit is proposed. The model can exhibit various nonlinear phenomena and responses to stimulation inputs. It is shown that the model can reproduce five types of inhibitory responses of Izhikevich's simplified ordinary differential equation neuron model. In addition, field programmable gate array experiments show that a learning algorithm enables the model to automatically reproduce nonlinear responses of a biological neuron and neuron models in the neuron simulator.

A novel automatic test pattern generator for asynchronous sequential digital circuits

A novel automatic test pattern generator (ATPG) for stuck-at faults of asynchronous sequential digital circuits is presented. The developed ATPG does not require support by any design-for-testability method nor external software tool. The shortest test sequence generation is guaranteed by breadth-first search. The contribution is unique hazard identification before the test generation process, state justification on the gate level, sequential fault propagation based on breadth-first search and stepwise composition of state graphs for sequential test generation. A new six-valued logic together with a new algorithm was developed for hazardous transition identification. The internal combinational ATPG allows to generate test patterns one by one and only if it is required by sequential test generation. The developed and implemented ATPG was tested with speed-independent and quasi-delay-insensitive benchmark circuits.

New Dimensions in Teaching Digital Electronics: A Multimode Laboratory Utilizing NI ELVIS IITM, LabVIEW and NI Multisim

Over the years, conventional Laboratories in African Universities have been hampered by inadequate resources in terms of the required hardware, space and skilled personnel to administer them. This paper describes a multi-dimensional approach to experimentation, developed by the Makerere University iLabs Project Team, hereafter referred to as iLABS@MAK. The two dimensional approach involves both Virtual Labs and Online Laboratories designed to address laboratory deficiencies in Digital Electronics, encompassing five courses in the curricula of the Bachelor of Science (B.Sc) in Computer, Electrical and Telecommunication Engineering Programs. A digital Online Laboratory, the Makerere University Digital iLab (MDEi) supporting experiments in the fields of combinational logic circuits and asynchronous sequential logic circuits has been developed. The laboratory utilizes the National Instruments Educational Laboratory Virtual Instrumentation Suite (NI ELVIS IIâ?¢) platform, the Laboratory Virtual Instrument Engineering Workbench (LabVIEW) graphical programming environment and NI Multisim. Typical experiment setups supported by the MDEi are presented

Asynchronous Sequential Machine Design and Analysis: A Comprehensive Development of the Design and Analysis of Clock-Independent State Machines and Systems

Asynchronous Sequential Machine Design and Analysis provides a lucid, in-depth treatment of asynchronous state machine design and analysis presented in two parts: Part I on the background fundamentals related to asynchronous sequential logic circuits generally, and Part II on self-timed systems, high-performance asynchronous programmable sequencers, and arbiters.Part I provides a detailed review of the background fundamentals for the design and analysis of asynchronous finite state machines (FSMs). Included are the basic models, use of fully documented state diagrams, and the design and characteristics of basic memory cells and Muller C-elements. Simple FSMs using C-elements illustrate the design process. The detection and elimination of timing defects in asynchronous FSMs are covered in detail. This is followed by the array algebraic approach to the design of single-transition-time machines and use of CAD software for that purpose, one-hot asynchronous FSMs, and pulse mode FSMs. Part I concludes with the analysis procedures for asynchronous state machines.Part II is concerned mainly with self-timed systems, programmable sequencers, and arbiters. It begins with a detailed treatment of externally asynchronous/internally clocked (or pausable) systems that are delay-insensitive and metastability-hardened. This is followed by defect-free cascadable asynchronous sequencers, and defect-free one-hot asynchronous programmable sequencers--their characteristics, design, and applications. Part II concludes with arbiter modules of various types, those with and without metastability protection, together with applications.Presented in the appendices are brief reviews covering mixed-logic gate symbology, Boolean algebra, and entered-variable K-map minimization. End-of-chapter problems and a glossary of terms, expressions, and abbreviations contribute to the reader's learning experience. Five productivity tools are made available specifically for use with this text and briefly discussed in the Preface.Table of Contents: I: Background Fundamentals for Design and Analysis of Asynchronous State Machines / Introduction and Background / Simple FSM Design and Initialization / Detection and Elimination of Timing Defects in Asynchronous FSMs / Design of Single Transition Time Machines / Design of One-Hot Asynchronous FSMs / Design of Pulse Mode FSMs / Analysis of Asynchronous FSMs / II: Self-Timed Systems/ Programmable Sequencers, and Arbiters / Externally Asynchronous/Internally Clocked Systems / Cascadable Asynchronous Programmable Sequencers (CAPS) and Time-Shared System Design / Asynchronous One-Hot Programmable Sequencer Systems / Arbiter Modules

Architecture and inherent robustness of a bacterial cell-cycle control system

A closed-loop control system drives progression of the coupled stalked and swarmer cell cycles of the bacterium Caulobacter crescentus in a near-mechanical step-like fashion. The cell-cycle control has a cyclical genetic circuit composed of four regulatory proteins with tight coupling to processive chromosome replication and cell division subsystems. We report a hybrid simulation of the coupled cell-cycle control system, including asymmetric cell division and responses to external starvation signals, that replicates mRNA and protein concentration patterns and is consistent with observed mutant phenotypes. An asynchronous sequential digital circuit model equivalent to the validated simulation model was created. Formal model-checking analysis of the digital circuit showed that the cell-cycle control is robust to intrinsic stochastic variations in reaction rates and nutrient supply, and that it reliably stops and restarts to accommodate nutrient starvation. Model checking also showed that mechanisms involving methylation-state changes in regulatory promoter regions during DNA replication increase the robustness of the cell-cycle control. The hybrid cell-cycle simulation implementation is inherently extensible and provides a promising approach for development of whole-cell behavioral models that can replicate the observed functionality of the cell and its responses to changing environmental conditions.

Radiation hardening by design

Historically, specialized foundry processes have been utilized to produce radiation hardened microelectronics. Radiation hardness by design techniques have been shown to be capable of producing devices of sufficient hardness to resist the deleterious effects of the natural radiation environment of space utilizing standard commercial processes. A description of the nature of radiation effects in microelectronics is presented followed by design techniques effective in mitigating single event effects in both static memory cells and combinational logic. A formal method based on the theory of asynchronous sequential circuits is used to analyse memory cells for recovery properties. A dual rail n-channel metal oxide semiconductor (NMOS) structure with a cross coupled output buffer dramatically reduces the susceptibility of combinational logic to propagation of single event transients.

Self-clocked sequential circuits: - a design example

Asynchronous sequential circuits offer improved speed of operation when compared to their synchronous counterparts. However, the standard methods of asynchronous design require careful examination of the flow table for possible critical races and hazards. This complicates the design procedure and often leads to extra states and additional hardware. A number of new design methodologies which involve locally generating a clock and using it to self synchronize the machine have been proposed. Such clock signals are generated whenever an input changes, or by controlled excitation whenever a change of inputs necessitates a change of state. All such designs, where the circuit is timed by locally generated clocks, are called Self-Clocked Sequential Circuits. This paper uses a design methodology for the State variable toggling through data driven clocks to implement a Direct Memory Access Controller (DMAC) as a design example. The design is simulated on software and also implemented using discrete hardware components. The methodology can be extended to parallel controllers for neural networks and automated using state assignment techniques already developed for synchronous parallel controllers. Keywords: Sequential circuits, synchronous, asynchronous, neural networks Botswana Journal of Technology Vol.13(1) 2004: 18-25

Checking combinational equivalence of speed-independent circuits

We introduce the notion of combinational equivalence to relate two speed-independent asynchronous (sequential) circuits: a “golden” hazard-free circuit C_1 and a “target” circuit C_2 that can be derived from C_1 through only combinational decomposition and extraction. Both circuits are assumed to be networks of single-output basic gates; multiple output gates such as arbiters, toggles, and dual-rail function blocks are not considered. We say that the circuits are combinationally equivalent if the decomposition and extraction preserves the essential functionality of the combinational blocks in the circuit and does not introduce hazards. The paper‘s focus is the bottleneck of the verification procedure, checking whether C_2 is hazard-free. We show that C_2 is hazard-free if and only if all of its signals are monotonic and acknowledged . We then show how cubes that approximate sets of reachable circuit states can be used to give sufficient conditions for monotonicity and acknowledgement. These sufficient conditions are used to develop a verification technique for combinational equivalence that can be exponentially faster than applying traditional, more general verification techniques. This result can be useful for verifying logic synthesis and technology mapping procedures.