Abstract
Asynchronous finite state machines are of great interest because they use fewer transistors to manufacture them. However, find the minimum resources in logic modeling is an NP-Problem, since the search space increase exponentially. Although this problem is studied for some time, there is still space for newer researches. Mostly, in new computational methods to improve performance in solving logical optimization in finite state machines. Thus, this paper presents a study and evaluation of heuristic algorithms for the optimization of asynchronous finite state machines, to obtain the smallest possible circuit. Thus, the Clause-Column Table and Quine-McCluskey algorithms are combined in order to propose an algorithm capable of minimizing asynchronous sequential circuits. Tests and results show that it is possible to synthesize circuits in a reasonable time, but with some logical errors. It may be concluded that it still needs research, even though it is not such a recent line of research.
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