Asynchronous SAR ADC Research Articles

Asynchronous SAR ADC with self‐timed track‐and‐hold

AbstractThis paper presents an asynchronous SAR ADC featuring a self‐timed track‐and‐hold (STH) architecture. The design aims to address the common timing issue of divider‐based clock generation, where the fixed‐time track‐and‐hold (FTH) period often results in incomplete conversions due to prolonged conversion times time due to comparator metastability. To alleviate the degradation of the ENOB induced by these delays, the proposed STH method is introduced so that more conversion period is secured without requiring a high‐speed input clock. Based on measurements, the proposed STH method achieves up to 0.7 bit improvement over the conventional FTH approach as conversion time increases.

SpacePix3: SOI MAPS detector for space radiation monitoring

The SpacePix3 monolithic active pixel sensor is a novel ASIC for space radiation monitoring designed in a 180 nm SOI CMOS technology. The detector is capable of detecting and differentiating protons, electrons, and heavy ions. Its active sensor area is 3.84×3.84 mm2, pixel matrix is arranged in a 64×64 square array with 60 µm pitch. The pixel front-end amplifier signal range is 1–80 ke-, extended up to 30 Me- using a backside channel. Diodes integrated in the handle wafer in each pixel are biased at -150 V, creating a depleted layer approximately 35 µm deep. Impinging particle generates a charge pulse converted to a voltage pulse by the charge-sensitive amplifier. Maximum voltage memorized by the peak detector hold circuit is digitized using on-chip 10-bit asynchronous column SAR ADCs. Two readout interfaces are available, 400 MHz LVDS and 50 MHz SPI. Total current consumption is 31 mA from a 1.8 V power supply in the SPI mode.

Method to Reduce the Number of Metastability Errors in Asynchronous SAR ADCs

A new approach is proposed to deal with the metastability errors in asynchronous SAR ADCs. This proposal avoids the disadvantages of conventional metastability detectors (additional metastability events due to the detector itself, slowness from additional comparator loading, additional logic delays, need to perform detection on each bit), but provides a significant decrease in metastability errors and their amplitudes. The approach uses both comparators’ outputs to detect whether metastability occurred at all during conversion (without determining in which particular bit). Theoretical examination and Octave simulation show that this information suffices to decrease the probability of errors with amplitudes > 2 LSB by an order.

SpacePix2: SOI MAPS detector for space radiation monitoring

The SpacePix2 monolithic active pixel sensor (MAPS) is a novel ASIC for space radiation monitoring designed in a 180 nm SOI CMOS technology. The active sensor area is 3.84 × 3.84 mm2, pixel matrix is arranged as a 64 × 64 array with 60 µm pitch. The pixel front-end amplifier signal range is 2–80 ke−, extended up to 30 Me− using a backside channel. Diodes integrated in the handle wafer in each pixel are biased at −150 V. Impinging particle generates a charge pulse converted to voltage pulse by charge sensitive amplifier (CSA). Maximum voltage memorized by the peak detector hold (PDH) circuit is digitized using on-chip 10-bit asynchronous column SAR ADCs. Two readout interfaces are available, 400 MHz LVDS and 50 MHz SPI. Total power consumption is 43 mA from a 1.8 V power supply. The ASIC has been tested in space in low Earth orbit (LEO) and sample data are shown.

Asynchronous capacitive SAR ADC based on Hopfield network

Asynchronous capacitive SAR ADC based on Hopfield network

A 516 μW, 121.2 dB-SNDR, and 125.1 dB-DR Discrete-Time Sigma-Delta Modulator with a 20 kHz BW

This article proposed a discrete-time single-loop 3rd order 5-bit Sigma-Delta (ΣΔ) modulator for the audio applications. In this modulator, a feed forward path is used to relax the design requirement of amplifier, which can reduce integrator’s output swing. And a 5-bit asynchronous SAR ADC combined with analog summing is adopted to quantify the summation of feedforward signal and loop filter output, which can significantly reduce power consumption. In addition, chopper stabilization technique is used to alleviate the flicker noise introduced by the first integrator. To eliminate the nonlinearity introduced by multibit quantizer, an improved data weighted average algorithm calibration circuit is proposed. The proposed modulator is implemented in 130 nm technology with a 1.12 mm2 core area. Operating at a 2.56MS/s sampling rate, post layout simulation results show that the modulator realizes 121.2-dB SNDR and 125.1-dB DR in a 20 kHz signal bandwidth, it dissipating 516 μW from 1.5 V supply. It also achieves the energy efficiency, as demonstrated by a Schreier figure of merit (FoMS) of 197 dB.

Onchip digital calibrated 2 mW 12-bit 25 MS/s SAR ADC with reduced input capacitance

We present a 12-bits asynchronous SAR ADC with a low complexity digital on-chip calibration and just 2 pF of total array capacitance. The ADC architecture utilizes a redundant weighting switching of 2 fF MOM capacitors consuming 14 clock-cycles to complete the conversion. Taking advantage of redundancy, the weights of the MSB capacitors are estimated using the LSB array, thus it is possible to digitally compensate for the mismatch non-linearity directly over the ADC output. The circuit consumes 2 mW at 25 MS/s on a core area of 300 μm × 500 μm in 180 nm CMOS technology. ENOB improvements of 0.85 bits were post-layout simulated after calibration. Sample characterization is ongoing.

A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application

A design of low-power 10-bit 1 MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) is presented in this paper. To improve the linearity of the digital-to-analog converter (DAC) and energy efficiency, a common mode-based monotonic charge recovery (CMMC) switching technique is proposed. The proposed switching technique consumes only 63.75 CVREF2 switching energy, which is far less as compared to the conventional switching technique without dividing or adding additional switches. In addition, bootstrap switching is implemented to ensure enhanced linearity. To reduce the power consumption from the comparator, a dynamic latch comparator with a self-comparator clock generation circuit is implemented. The proposed prototype of the SAR ADC is implemented in a 55 nm CMOS (complementary metal-oxide-semiconductor) process. The proposed architecture achieves a figure of merit (FOM) of 17.4 fJ/conversion, signal-to-noise distortion ratio (SNDR) of 60.39 dB, and an effective number of bits (ENOB) of 9.74 bits with a sampling rate of 1 MS/s at measurement levels. The implemented SAR ADC consumes 14.8 µW power at 1 V power supply.

An AC-Coupled Wideband Neural Recording Front-End With Sub-1 mm2×fJ/conv-step Efficiency and 0.97 NEF

This letter presents an energy-and-area-efficient ac-coupled front-end for the multichannel recording of wideband neural signals. The proposed unit conditions local field and action potentials using an inverter-based capacitively coupled low-noise amplifier, followed by a per-channel 10-b asynchronous SAR ADC. The adaptation of unit-length capacitors minimizes the ADC area and relaxes the amplifier gain so that small coupling capacitors can be integrated. The prototype in 65-nm CMOS achieves $4\times $ smaller area and $3\times $ higher energy–area efficiency compared to the state of the art with 164 $\mu \text{m}\times 40\,\,\mu \text{m}$ footprint and 0.78 mm $^{2}\times $ fJ/conv-step energy-area figure of merit. The measured 0.65- $\mu \text{W}$ power consumption and 3.1 - $\mu \text{V}_{\mathrm{ rms}}$ input-referred noise within 1 Hz–10 kHz bandwidth correspond to a noise efficiency factor of 0.97.

A 2.18-pJ/conversion, 1656-μm² Temperature Sensor With a 0.61-pJ·K² FoM and 52-pW Stand-By Power

This letter describes a miniature, ultra low power, all-dynamic temperature sensor based on a duty-cycled resistive transducer bridge and a 9-bit asynchronous SAR ADC in 65-nm CMOS. It features a novel floating bridge technique and automatic power gating to achieve the lowest reported power consumption. It consumes 2.18 pJ per conversion and has an RMS resolution of 0.53 K, leading to an FoM of 0.61 pJ·K <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . A standby power of 52 pW allows a high power-efficiency, even at low sample rates. It occupies 36×46 μm of chip area and has a sensing range from -20 °C to 120 °C.

A Resolution-Reconfigurable Asynchronous SAR ADC with Segmented and Non-Binary Weighted Capacitance DACs

A Resolution-Reconfigurable Asynchronous SAR ADC with Segmented and Non-Binary Weighted Capacitance DACs

A 10-bit 10-MS/s single-ended asynchronous SAR ADC with CDAC boosting common-mode voltage and controlling input voltage range

A 10-bit 10-MS/s single-ended asynchronous SAR ADC with CDAC boosting common-mode voltage and controlling input voltage range

On the design of high-speed energy-efficient successive-approximation logic for asynchronous SAR ADCs**Project supported by the National Natural Science Foundation of China (Nos. 61204033, 61331015), the Fundamental Research Funds for the Central Universities (No. WK2100230015), and the Funds of Science and Technology on Analog Integrated Circuit Laboratory (No. 9140C090111150C09041).

This paper analyzes the power consumption and delay mechanisms of the successive-approximation (SA) logic of a typical asynchronous SAR ADC, and provides strategies to reduce both of them. Following these strategies, a unique direct-pass SA logic is proposed based on a full-swing once-triggered DFF and a self-locking tri-state gate. The unnecessary internal switching power of a typical TSPC DFF, which is commonly used in the SA logic, is avoided. The delay of the ready detector as well as the sequencer is removed from the critical path. A prototype SAR ADC based on the proposed SA logic is fabricated in 130 nm CMOS. It achieves a peak SNDR of 56.3 dB at 1.2 V supply and 65 MS/s sampling rate, and has a total power consumption of 555 μW, while the digital part consumes only 203 μW.

Analysis of Metastability Errors in Conventional, LSB-First, and Asynchronous SAR ADCs

A practical model for characterizing comparator metastability errors in SAR ADCs is presented, and is used to analyze not only the conventional SAR but also LSB-first and asynchronous versions. This work makes three main contributions: first, it is shown that for characterizing metastability it is more reasonable to use input signals with normal or Laplace distributions. Previous work used uniformly-distributed signals in the interest of making derivations easier, but this simplifying assumption overestimated SMR by as much as 18 dB compared to the more reasonable analysis presented here. Second, this work shows that LSB-first SAR ADCs achieve SMR performance equal to or better than conventional SARs with the same metastability window, depending on bandwidth. Finally, the analysis is used to develop a framework for calculating the maximum effective sample rate for asynchronous SAR ADCs, and in doing so demonstrates that proximity detectors are not effective solutions to improving metastability performance.

A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65 nm CMOS

A 10-bit 300-MS/s asynchronous SAR ADC in 65nm CMOS is presented in this paper. To achieve low power, binary-weighed capacitive DAC is employed without any digital correction or calibration. Consequently, settling time for the capacitive DAC would be a dominant limiting factor for the ADC operating speed. A novel architecture is proposed to optimize the settling time for the capacitive DAC, which depends merely on the on-resistance of switches and the capacitance of unit capacitor and irrelevant to the resolution. Therefore, high-speed high-resolution SAR ADC is possible. What is deserved to highlight is that the architecture improves the ADC performance at a fraction of the cost, with only some capacitors and control logic added. Post-layout simulation has been made for the SAR ADC. At a 1.2-V supply voltage and a sampling rate of 300MS/s, it consumes 1.27mW and achieves an SNDR of 60dB, an SFDR of 67.5dB, with the Nyquist input. The SAR ADC occupies a core area of 450×380μm2.

A single channel, 6-bit 410-MS/s 3bits/stage asynchronous SAR ADC based on resistive DAC**Project supported by the National Science Foundation for Young Scientists of China (No. 61306029) and the National High Technology Research and Development Program of China (No. 2013AA014103).

This paper presents a single channel, low power 6-bit 410-MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) for ultrawide bandwidth (UWB) communication, prototyped in a SMIC 65-nm process. Based on the 3 bits/stage structure, resistive DAC, and the modified asynchronous successive approximation register control logic, the proposed ADC attains a peak spurious-free dynamic range (SFDR) of 41.95 dB, and a signal-to-noise and distortion ratio (SNDR) of 28.52 dB for 370 MS/s. At the sampling rate of 410 MS/s, this design still performs well with a 40.71-dB SFDR and 30.02-dB SNDR. A four-input dynamic comparator is designed so as to decrease the power consumption. The measurement results indicate that this SAR ADC consumes 2.03 mW, corresponding to a figure of merit of 189.17 fJ/step at 410 MS/s.

A 7-bit 40 MS/s single-ended asynchronous SAR ADC in 65 nm CMOS

This paper presents a 7-bit 40 MS/s single-ended asynchronous SAR ADC intended for in-probe use in medical applications, which requires small area and good power efficiency. A single-ended architec...

A single-channel 8-bit 660 MS/s asynchronous SAR ADC with pre-settling procedure in 65 nm CMOS

A single-channel 8-bit low-power high-speed SAR ADC with a novel pre-settling procedure is presented in this paper. The proposed procedure relaxes the settling time significantly and improves the speed of the ADC. Moreover, the asynchronous technique avoids the high frequency internal clocks and further increases the speed of the SAR ADC. Based on SMIC 65nm 1.2-V CMOS technology, the simulation results demonstrate that DNL and INL are −0.4/0.4LSBs and −0.9/0.8 LSBs, respectively. At 660MS/s sampling rate, the ADC consumes 7.6mW from a 1.2V supply. The proposed SAR ADC׳s SNDR and SFDR are 49.5dB and 64.2dB, respectively.

A 0.5-V 5.2-fJ/Conversion-Step Full Asynchronous SAR ADC With Leakage Power Reduction Down to 650 pW by Boosted Self-Power Gating in 40-nm CMOS

This paper presents an ultralow-power and ultralow-voltage SAR ADC. Full asynchronous operation and boosted self-power gating are proposed to improve conversion accuracy and reduce static leakage power. By designing with MOSFET of high threshold voltage (HV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> ) and low threshold voltage (LV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> ), the leakage power is reduced without decrease of maximum sampling frequency. The test chip in 40-nm CMOS process has successfully reduced leakage power by 98%, and it achieves 8.2-bit ENOB and while consuming only 650 pW at 0.1 kS/s from 0.5-V power supply. The power consumption is scalable up to 4 MS/s and power supply range from 0.4 to 0.7 V. The best figure of merit at 0.5 V is 5.2 fJ/conversion-step at 20 kS/s.

A 4-10bit, 0.4-1V Power Supply, Power Scalable Asynchronous SAR-ADC in 40nm-CMOS with Wide Supply Voltage Range SAR Controller

A 4-10bit, 0.4-1V Power Supply, Power Scalable Asynchronous SAR-ADC in 40nm-CMOS with Wide Supply Voltage Range SAR Controller