A single-channel 8-bit 660 MS/s asynchronous SAR ADC with pre-settling procedure in 65 nm CMOS

Abstract

A single-channel 8-bit low-power high-speed SAR ADC with a novel pre-settling procedure is presented in this paper. The proposed procedure relaxes the settling time significantly and improves the speed of the ADC. Moreover, the asynchronous technique avoids the high frequency internal clocks and further increases the speed of the SAR ADC. Based on SMIC 65nm 1.2-V CMOS technology, the simulation results demonstrate that DNL and INL are −0.4/0.4LSBs and −0.9/0.8 LSBs, respectively. At 660MS/s sampling rate, the ADC consumes 7.6mW from a 1.2V supply. The proposed SAR ADC׳s SNDR and SFDR are 49.5dB and 64.2dB, respectively.