Asynchronous Circuits Research Articles

Beyond classification: directly training spiking neural networks for semantic segmentation

Spiking neural networks (SNNs) have recently emerged as the low-power alternative to artificial neural networks (ANNs) because of their sparse, asynchronous, and binary event-driven processing. Due to their energy efficiency, SNNs have a high possibility of being deployed for real-world, resource-constrained systems such as autonomous vehicles and drones. However, owing to their non-differentiable and complex neuronal dynamics, most previous SNN optimization methods have been limited to image recognition. In this paper, we explore the SNN applications beyond classification and present semantic segmentation networks configured with spiking neurons. Specifically, we first investigate two representative SNN optimization techniques for recognition tasks (i.e., ANN-SNN conversion and surrogate gradient learning) on semantic segmentation datasets. We observe that, when converted from ANNs, SNNs suffer from high latency and low performance due to the spatial variance of features. Therefore, we directly train networks with surrogate gradient learning, resulting in lower latency and higher performance than ANN-SNN conversion. Moreover, we redesign two fundamental ANN segmentation architectures (i.e., Fully Convolutional Networks and DeepLab) for the SNN domain. We conduct experiments on three semantic segmentation benchmarks including PASCAL VOC2012 dataset, DDD17 event-based dataset, and synthetic segmentation dataset combined CIFAR10 and MNIST datasets. In addition to showing the feasibility of SNNs for semantic segmentation, we show that SNNs can be more robust and energy-efficient compared to their ANN counterparts in this domain.

Neuromorphic Functional Modules of a Spiking Neural Network

In the current era, the design and development of artificial neural networks exploiting the architecture of the human brain have evolved rapidly. Artificial neural networks (ANN) effectively solve a wide range of common artificial-intelligence tasks involving data classification and recognition, prediction, forecasting and adaptive control of the behavior of an object. The biologically inspired underlying principles of ANN operation have certain advantages over the conventional von Neumann architecture including unsupervised learning, architectural flexibility and adaptability to environmental change and high performance under significantly reduced power consumption due to large parallel and asynchronous data processing. In this paper, we present a circuit design of main functional blocks (neurons and synapses) intended for the hardware implementation of a perceptron-based feedforward spiking neural network. As the third generation of artificial neural networks, spiking neural networks perform data processing utilizing spikes, which are discrete events (or functions) that take place at points in time. Neurons in spiking neural networks initiate precisely timed spikes and communicate with each other via spikes transmitted through synaptic connections or synapses with adaptable scalable weight. One of the prospective approaches to emulating synaptic behavior in hardware implemented spiking neural networks is to use nonvolatile-memory devices with analog conduction modulation (or memristive structures). Here we propose a circuit design for functional analogues of memristive structures to mimic synaptic plasticity, pre- and postsynaptic neurons which could be used for developing a circuit design of spiking-neural-network architectures with different training algorithms including the spike-timing-dependent-plasticity learning rule. Two different circuits of an electrical synapse are developed. The first one is an analog synapse with a photoresistor optocoupler used to ensure the tunable conductivity for synaptic-plasticity emulation. While the second one is a digital synapse, in which the synaptic weight is stored in a digital code with its direct conversion into conductivity (without a digital-to-analog converter and photoresistor optocoupler). The results of prototyping the developed circuits for electronic analogs of synapses, pre- and postsynaptic neurons and the study of transient processes are presented. The developed approach could provide a basis for the ASIC (application-specific integrated circuit) design of spiking neural networks based on CMOS (complementary metal—oxide–semiconductor) design technology.

Muller C-Element Exploiting Programmable Metallization Cell for Bayesian Inference

Decision-making via Bayesian inference is a prominent operation in several autonomous applications, including robotics, brain-machine interactions, artificial intelligence (AI) agents, etc. A cascaded tree of asynchronous logic elements, known as Muller C-elements, can perform stochastic Bayesian inference efficiently. Therefore, there is an urgent need for compact and energy-efficient Muller C-element realizations. To this end, in this work, for the first time, we propose a Muller C-element utilizing a Programmable Metallization Cell (PMC) and a CMOS inverter. Using an experimentally calibrated, in-house developed physics-based compact model of Ag-Ge0.3Se 0.7 PMC and CMOS inverter (in 7 nm technology node), we show that the proposed Muller C-element is extremely compact and consumes at least <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 9\times $ </tex-math></inline-formula> less power compared to the previously reported implementations. Furthermore, we demonstrate that the proposed PMC-based Muller C-element can make Bayesian inferences on bitstream-encoded data with reasonable accuracy. Our results indicate that the computational precision depends significantly on the number of output bits and the probability encoded by the inputs to the Muller C-element. Moreover, we also propose a novel readout circuit design to facilitate cascading of multiple PMC-based Muller C-elements to increase the number of evidence sources and demonstrate its efficacy for spam filtering applications.

Wave Pipelining in DSFQ Circuits

Dynamic SFQ (DSFQ) circuits are a promising form of asynchronous SFQ logic. The operation of DSFQ circuits, however, significantly differs from both CMOS logic and conventional synchronous RSFQ logic. Novel design methodologies are necessary to synthesize DSFQ circuits, while increasing performance and decreasing area. The path balancing process, essential for RSFQ circuits, is less important for DSFQ. Path delay balancing can, however, increase the performance of DSFQ circuits by enabling wave pipelining. In this article, several path balancing approaches for DSFQ circuits are evaluated and compared to equivalent RSFQ circuits. A partial path balancing methodology is described, where path balancing is primarily applied to the inputs of those gates with significant input skew. This methodology provides an effective tradeoff between system performance and area and enables wave pipelining in small to medium scale combinatorial DSFQ circuits without feedback, reducing the period between data waves.

High-level Modeling and Verification Platform for Elastic Circuits with Process Variation Considerations

In addition to the advantages of asynchronous circuits, compatibility with synchronous EDA tools is another strength point of synchronous elastic circuits. Synchronous elastic circuits face some challenges, such as process variations that can compromise its performance and functionality, and the multitude of available implementations based on elastic elements’ combinations, meaning that choosing the best combination could not be simple. In this paper, a novel method is introduced to model and verify synchronous elastic circuits in the presence of variations. The model is based on xMAS, which is a new formal modeling paradigm to synthesize, test, and verify circuits and networks. In this method, various elastic elements are modeled and available in the form of a library in xMAS, so the designer can build complicated elastic circuits by combining different elastic elements. Additionally, by translating a high-level xMAS model into a SAN statistical model and using its capabilities, elements’ internal delays will be embedded, which makes the high-level modeling and elastic circuits’ high-resolution time analysis available. Based on the obtained results, elastic circuits are highly capable of tolerating variations. However, this phenomenon could lead to a maximum of 2.35% error in synchronization control units and data in these circuits.

General Approach to Asynchronous Circuits Simulation Using Synchronous FPGAs

Using field-programmable gate arrays (FPGAs) for software and hardware verification and development is a standard step in the digital application-specific integrated circuits (ASICs) design flow. However, asynchronous FPGAs are not available on the market and commercially available FPGAs provide support only for synchronous circuits. Although a lot of research effort has been undertaken in order to use synchronous FPGA to map asynchronous circuits, proposed solutions are typically lacking automation and target-specific circuit style and sometimes specific FPGA vendor. In this work, we present an automated solution for asynchronous circuits mapping onto the synchronous FPGAs. We build a synchronous model of the original asynchronous circuit based on the event-driven simulation concepts. The proposed approach supports a wide range of circuit styles, including those with various timing assumptions and complex circuitry structures incompatible with the standard synchronous flow. We avoid using vendor-specific features so that the model we generate can be implemented on any commercially available FPGA. We provide an extensive evaluation of our solution and demonstrate that our approach results in a speedup factor of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.3\times 10^{5}$ </tex-math></inline-formula> against an asynchronous circuit simulator, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.8\times 10^{4}$ </tex-math></inline-formula> against commercial digital simulators, and is 16.5 times slower than the expected performance of the original asynchronous circuit implemented as an ASIC.

Versatile DAC-less successive approximation ADC architecture for medium speed data acquisition

Implementation of the DAC is usually the bottleneck in designing a SAR ADC. Here an innovative DAC-less SAR (DLSAR) ADC architecture is presented which alleviates some drawbacks of the conventional SAR counterpart. The proposed DLSAR binary search algorithm is comprised of two arithmetic operations of division-by-two and subtraction to emulate the DAC function. The hardware of the DLSAR ADC is implemented using ordinary circuit building blocks of a SAR ADC but with less complexity and more robustness against PVT variations as DAC is removed. The developed DLSAR architecture is versatile so that the converter hardware could be readily reconfigured for different sampling rates and resolutions. Based on post-layout simulations in 0.18 μm CMOS process, the designed 8-bit DLSAR ADC consumes 150 μW of power at 2 MS/s including the asynchronous control logic circuit. The SFDR of the converter is up to 62 dB and the ENOB reaches 7.8 bits while it remains above 7.5 bits across most PVT corners without calibration. Also, by reconfiguring the DLSAR ADC to 9-bit resolution at 1 MS/s, the ENOB is generally around 8.2 bits achieving a scaled figure-of-merit (SFoM) better than 3.0 Ç/c-s.

PELATIHAN MATERI KURIKULUM OPERASIONAL SATUAN PENDIDIKAN BAGIAN 1 BAGI KOMITE PEMBELAJARAN SEKOLAH PENGGERAK ANGKATAN 2

This community development activity is facilitated by the Ministry of Education, Culture, Research and Technology which organizes the Institute for the Development and Empowerment of Principals (LPPKSPS) in the form of training activities for the learning committee (PKP) in Sekolah Penggerak Batch 2. The series of modules that must be studied by PKP are: Education Unit Operational Curriculum (KOSP) module series Part 1. The method used in this activity is service learning with synchronous and asynchronous designs. Asynchronous sessions are activities of participants in the Learning Management System (LMS) to study material before joining the virtual space of gmeet in a synchronous session. This community development shows that the participants are able to independently analyze the characteristics that form the basis for the preparation of the vision, mission and goals of the educational unit/school. In addition, participants showed an understanding of the importance of the vision, mission, goals that are in accordance with the characteristics and needs of the education unit/school that are in line with the achievement of national education goals, then participants also understand the importance of the involvement of all school/educational units in the formulation of the vision, mission and goals of the education unit.

A 12bit 250 MS/s 5.43fJ/conversion-step SAR ADC with adaptive asynchronous logic in 28 nm CMOS

A 12-bit 250-MS/s adaptive asynchronous successive approximation registers analog-to-digital converter (SAR ADC) with a Non-binary segmented split capacitor array is proposed. The Non-binary bridge split capacitor array leads to much larger units with reduced total capacitance and allows for reducing digital-to-analog converter (DAC) settling time and power consumption. The reset time of the comparator is automatically and precisely adjusted according to the settling time required by each capacitor of the non-binary capacitor array, which accelerates the ADC quantization. With the proposed adaptive asynchronous logic (AAL), the settling time utilization will reach 98.6% and the overall ADC's speed can be increased by 30%. The circuit was designed in 28 nm CMOS technology. The mismatch of the capacitor is calibrated by the Least Mean Square (LMS) background calibration for high speed and low power consumption. Based on post-layout simulations, the ADC achieves a signal-to-noise distortion ratio (SNDR) of 67.92 dB at 250 MS/s sampling rate and consumes 2.76 mW, resulting in a figure of merit of 5.43fJ/conversion-step. The ADC core occupies an active area of only 100 μm × 350 μm.

An Asynchronous Bundled-Data Template With Current Sensing Completion Detection Technique

An asynchronous circuit design paradigm can address the increasing energy efficiency and speed demands of portable electronic devices. However, designing a low-cost event-driven asynchronous circuitry is a challenging task. In this brief, we propose a novel asynchronous bundled-data event-driven template created by using the current sensing completion detection (CSCD) technique. The proposed template has the advantages of the cost-efficient characteristics of bundled-data circuits without suffering the disadvantages of PVT-sensitive matching delay cells. An asynchronous RISC-V processor was designed and thoroughly compared with its synchronous counterpart and the popular RISC-V cores to validate the effectiveness of the proposed template. The asynchronous processor delivers the same performance as the synchronous counterpart while consuming only 80.09% of the power. Alternatively, the asynchronous processor achieves a 1.32x speedup under the same power consumption. In addition, the asynchronous processor leverages 1.48x-3.23x energy efficiency against the other popular RISC-V cores.

Illegal Trojan design and detection in asynchronous NULL Convention Logic and Sleep Convention Logic circuits

With Cyber warfare, detection of hardware Trojans, malicious digital circuit components that can leak data and degrade performance, is an urgent issue. Quasi-Delay Insensitive asynchronous digital circuits, such as NULL Convention Logic (NCL) and Sleep Convention Logic, also known as Multi-Threshold NULL Convention Logic (MTNCL), have inherent security properties and resilience to large fluctuations in temperatures, which make them very alluring to extreme environment applications, such as space exploration, automotive, power industry etc. This paper shows how dual-rail encoding used in NCL and MTNCL can be exploited to design Trojans, which would not be detected using existing methods. Generic threat models for Trojans are given. Formal verification methods that are capable of accurate detection of Trojans at the Register-Transfer-Level are also provided. The detection methods were tested by embedding Trojans in NCL and MTNCL Rivest-Shamir-Adleman (RSA) decryption circuits. The methods were applied to 25 NCL and 25 MTNCL RSA benchmarks of various data path width and provided 100% rate of detection.

LASER DRILLING OF AIR-FILM COOLING HOLES IN AIR AND WITH COAXIAL WATERJET ASSISTANCE

Air-film cooling holes were drilled into a turbine blade with a 532-nm Nd:YVO4 nanosecond laser in air and with coaxial waterjet assistance. The drilling quality of the sidewalls of the holes was investigated comparatively by means of a 3D confocal laser scanning microscope, scanning electron microscopy, transmission electron microscopy, X-ray diffraction and energy-dispersive X-ray spectroscopy. Results have shown that the maximum thickness of the processing-induced defects around the air-film cooling holes drilled by the laser in air is up to 100 µm, while the holes obtained by means of the asynchronous operation of laser drilling in air and coaxial waterjet assistance indicate no spatter, oxide layer, recast layer or cracks. Compared with laser drilling in air, the minimum size of the heat-affected zone around the air-film cooling holes induced by asynchronous processing is decreased down to the sub-micrometer scale. The main phases in the oxide layer, recast layer and heat-affected zone are α-Al2O3, γ-Ni, and β-NiAl, respectively. Asynchronous processing can help us achieve high position precision and it will have wide application.&#x0D; are α-Al2O3, γ-Ni, and β-NiAl, resp

An asynchronous artifact-enhanced electroencephalogram based control paradigm assisted by slight facial expression.

In this study, an asynchronous artifact-enhanced electroencephalogram (EEG)-based control paradigm assisted by slight-facial expressions (sFE-paradigm) was developed. The brain connectivity analysis was conducted to reveal the dynamic directional interactions among brain regions under sFE-paradigm. The component analysis was applied to estimate the dominant components of sFE-EEG and guide the signal processing. Enhanced by the artifact within the detected electroencephalogram (EEG), the sFE-paradigm focused on the mainstream defect as the insufficiency of real-time capability, asynchronous logic, and robustness. The core algorithm contained four steps, including “obvious non-sFE-EEGs exclusion,” “interface ‘ON’ detection,” “sFE-EEGs real-time decoding,” and “validity judgment.” It provided the asynchronous function, decoded eight instructions from the latest 100 ms signal, and greatly reduced the frequent misoperation. In the offline assessment, the sFE-paradigm achieved 96.46% ± 1.07 accuracy for interface “ON” detection and 92.68% ± 1.21 for sFE-EEGs real-time decoding, with the theoretical output timespan less than 200 ms. This sFE-paradigm was applied to two online manipulations for evaluating stability and agility. In “object-moving with a robotic arm,” the averaged intersection-over-union was 60.03 ± 11.53%. In “water-pouring with a prosthetic hand,” the average water volume was 202.5 ± 7.0 ml. During online, the sFE-paradigm performed no significant difference (P = 0.6521 and P = 0.7931) with commercial control methods (i.e., FlexPendant and Joystick), indicating a similar level of controllability and agility. This study demonstrated the capability of sFE-paradigm, enabling a novel solution to the non-invasive EEG-based control in real-world challenges.

MORPHOLOGICAL SPATIAL PATTERN ANALYSIS: OPEN SOURCE RELEASE

Abstract. The morphological segmentation of binary patterns provides an effective method for characterising spatial patterns with emphasis on connections between their parts as measured at varying analysis scales. The method is widely used for the analysis of landscape patterns such as those related to the fragmentation of forests or other natural land cover classes. This can be explained by its effectiveness at capturing the complexity of binary patterns and their connections by partitioning the foreground pixels of the corresponding binary images into mutually exclusive classes. While the principles of the method are conceptually simple, the definition of the classes relies on a series of advanced mathematical morphology operations whose actual implementation is not straightforward. In this paper, we propose an open source code for MSPA and detail its main components in the form of pseudo-code. We demonstrate its effectiveness for asynchronous processing of tera-pixel images and the synchronous exploratory analysis and rendering with Jupyter notebooks.

Asynchronous Background Processing for accelerated simulation of wireless communication on multi-core systems

Discrete event simulation (DES) is an important tool for the development and analysis of wireless networks. However, with increasing network size and complexity, the computational effort and simulation time increases significantly, often exponentially. This increase in response time may be critical if DES is interfacing real-time systems like Hardware in the Loop (HIL) or network emulation. It also slows down development cycles of users designing or debugging simulation models. Most popular DES software packages run single-threaded. Thus, they achieve only limited performance improvements from more modern multi-core CPUs. At the same time, existing approaches for parallel simulation of networks do not perform well on wireless systems or require complex paradigm shifts in simulation models. In this paper, we propose Asynchronous Background Processing (ABP) to accelerate the simulation of wireless communication on multi-core systems. By moving expensive computation from the main thread into asynchronous tasks computed by background threads, it accelerates the progression of events and thus reduces response time. Tasks are started as early as possible to exploit the time the main thread spends processing other events, ideally providing results before they are needed in the simulation. We showcase the application of ABP using Veins, a popular vehicular network simulator, demonstrating speedups of up to 3.5 on typical desktop platforms. We further perform an in-depth analysis using advanced profiling techniques to investigate the effectiveness of the parallelization and guide further optimizations.

Static Timing Analysis for Single-Flux-Quantum Circuits Composed of Various Gates

Superconductive single-flux-quantum (SFQ) circuits operate with very high clock frequency and its timing design is a difficult task. In circuit design, static timing analysis (STA) is a key process for evaluating and verifying the timing of a circuit design. Conventional timing analysis for SFQ circuits focuses on circuits composed of clocked gates and splitters; however, practical SFQ circuits are composed of various gates, i.e., not only clocked gates but also other gates, such as nondestructive read-out, confluence buffer, and clockless logic gates. In this article, to express timing constraints of both clocked gate cells and other cells, we define timing requirements of cells as minimum and maximum acceptable intervals on ordered pairs of input pins. Via these, we express timing constraints of cells in an SFQ circuit design. Furthermore, to eliminate unnecessary pessimism during variation-aware timing analysis, we propose a method of common path pessimism removal (CPPR) for SFQ circuits composed of various cells. We implement an STA tool using the defined timing constraints and the CPPR method. The experimental results show that our STA tool verifies the timing of SFQ circuits composed of various cells.

A Design of 10-Bit Asynchronous SAR ADC with an On-Chip Bandgap Reference Voltage Generator.

A proposed prototype of a 10-bit 1 MS/s single-ended asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with an on-chip bandgap reference voltage generator is fabricated with 130 nm technology. To optimize the power consumption, static, and dynamic performance, several techniques have been proposed. A dual-path bootstrap switch was proposed to increase the linearity sampling. The Voltage Common Mode (VCM)-based Capacitive Digital-to-Analog Converter (CDAC) switching technique was implemented for the CDAC part to alleviate the switching energy problem of the capacitive DAC. The proposed architecture of the two-stage dynamic latch comparator provides high speed and low power consumption. Moreover, to achieve faster bit conversion with an efficient time sequence, asynchronous SAR logic with an internally generated clock is implemented, which avoids the requirement of a high-frequency external clock, as all conversions are carried out in a single clock cycle. The proposed error amplifier-based bandgap reference voltage generator provides a stable reference voltage to the ADC for practical implementation. The measurement results of the proposed SAR ADC, including an on-chip bandgap reference voltage generator, show an Effective Number of Bits (ENOB) of 9.49 bits and Signal-to-Noise and Distortion Ratio (SNDR) of 58.88 dB with 1.2 V of power supply while operating with a sampling rate of 1 MS/s.

A Minimal Buffer Router with Level Encoded Dual Rail-Based Design of Network-on-Chip Architecture

Asynchronous NOCs are most prominent in present SOC designs, due to their low dynamic power consumption, modularity, heterogeneous nature, and robustness to the process variations. Though asynchronous designs are proved efficient over synchronous counterparts, they have some severe drawbacks when area and speed are considered, due to complex handshake control circuits which increase the static power loss. Quasidelay insensitive (QDI) class of asynchronous NOCs based on 2-phase encoding is proved beneficial for speed and throughput enhancement but with complex design. The work has introduced lightweight minimal buffer router based on LEDR encoding to design a low power, high speed with compact NOC architecture. Then, minimal buffer router with FSM-based arbiter and priority assigner block is designed to enhance the speed, power, and area. This proposed work achieves zero dynamic power consumption with a total power consumption of less than 0.082 W with a router latency of 0.8 ns.

THx2 Programmable Logic Block Architecture for Clockless Asynchronous FPGAs

To address some of the challenges of asynchronous design, we propose a new, decomposable asynchronous logic block architecture based on our TH<inline-formula> <tex-math notation="LaTeX">$x2$ </tex-math></inline-formula> programmable threshold cell, and we use it to implement common threshold functions found in asynchronous, null convention logic circuits. At a minimum, programmable gate arrays require a programmable logic cell that can implement a complete set of logic. It is well known that a NAND function forms a complete set of logic, and in null convention logic, the TH12 and TH22 threshold cells are used to form a basic two-input NAND function. The TH<inline-formula> <tex-math notation="LaTeX">$x2$ </tex-math></inline-formula> threshold cell is capable of performing both TH12 and TH22 operations, so it too forms a complete set of logic. In this paper, we present our eight-transistor mask-programmable gate array logic cell, 16-transistor field-programmable gate array logic cell, and new decomposable field-programmable gate array logic block architecture, all based on the TH<inline-formula> <tex-math notation="LaTeX">$x2$ </tex-math></inline-formula> threshold cell and suitable for implementing null convention logic asynchronous functions. To minimize the TH<inline-formula> <tex-math notation="LaTeX">$x2$ </tex-math></inline-formula> threshold cell area for both TH12 and TH22 modes, we designed a layout with common Euler paths and no diffusion breaks for both modes. The highly compact nature of the TH<inline-formula> <tex-math notation="LaTeX">$x2$ </tex-math></inline-formula> threshold cell&#x2013;along with the symmetry of the mask- and field-programmable gate array logic cells&#x2013;made it an ideal candidate for an asynchronous field-programmable logic block structure. This paper is part of an ongoing project, and it only addresses the programmable logic block architecture, not a complete FPGA fabric.

A Methodology to Design Static NCL Libraries

The Null Convention Logic (NCL) based asynchronous design technique has interested researchers because this technique had overcome disadvantages of the synchronous technique, such as noise, glitches, clock skew and power. However, using the NCL-based asynchronous design method is difficult for university students and researchers because of the lack of standard NCL cell libraries. Therefore, in this paper, a novel flow is proposed to design NCL cell libraries. These libraries are used to synthesize NCL-based asynchronous designs. We chose the static NCL cell library to illustrate the proposed design solution because this library is one of the most basic NCL libraries. Static NCL cells in this library are designed based on the Process Design Kit 45nm technology and are implemented by the Virtuoso and the Design Compiler (DC) tool. In addition, the Ocean script and Electronic Design Automation (EDA) environment are used for supporting designs and simulations. A complete library of 27 NCL cells was designed to serve for study and research. We also implemented synthesis for NCL full adders using this library and compared our synthesis results with the results of other authors. The comparison results indicated that our results were a 20% improvement on power consumption.