Wave Pipelining in DSFQ Circuits

Abstract

Dynamic SFQ (DSFQ) circuits are a promising form of asynchronous SFQ logic. The operation of DSFQ circuits, however, significantly differs from both CMOS logic and conventional synchronous RSFQ logic. Novel design methodologies are necessary to synthesize DSFQ circuits, while increasing performance and decreasing area. The path balancing process, essential for RSFQ circuits, is less important for DSFQ. Path delay balancing can, however, increase the performance of DSFQ circuits by enabling wave pipelining. In this article, several path balancing approaches for DSFQ circuits are evaluated and compared to equivalent RSFQ circuits. A partial path balancing methodology is described, where path balancing is primarily applied to the inputs of those gates with significant input skew. This methodology provides an effective tradeoff between system performance and area and enables wave pipelining in small to medium scale combinatorial DSFQ circuits without feedback, reducing the period between data waves.