Asynchronous Array Research Articles

An investigation of the performances of asynchronous measurements methods

In acoustical imaging and source localization, several methods for the exploitation of asynchronous array measurements have been proposed, based on covariance matrix completion, Bayesian estimation, fusion of beamforming maps, etc. The goal of asynchronous measurements is to reach the performance of large and dense arrays, with reduced experimental effort, by moving an array of limited size between experiments, and fuse the obtained data to produce an estimation of the distribution of acoustical sources. In this study, we consider the performances that one can expect from asynchronous measurements, and investigate the actual performances of several methods from the state of the art. In particular, the mean squared errors of the estimation of the position and power of an acoustical source are estimated using simulations and experimental measurements.

Voltage Stacking: A First-Order Modelization of an m × n Asynchronous Array for Chip and Architectural Design Exploration

Voltage stacking is a technique in which multiple integrated circuits are stacked in series between the supply voltage instead of in parallel, thus improving the energy efficiency of the power distribution network. Unfortunately, voltage stacking presents stability challenges for integrated circuits within the stack. A first-order model to quantify variability, stability, and power metrics for an array of voltage-stacked asynchronous integrated circuits is presented. Voltage variability and power consumption are accounted for and discussed. Limitations of the model are identified outside of the nominal behavior. The number of columns in the architecture, chip leakage, and supply voltage are shown to be the key contributors to the stability, performance, and energy efficiency of a system of voltage-stacked asynchronous processors. A higher leakage to active power ratio, though usually avoided by chip designers, is shown to improve stability and be key in designing stacks without external balancing. Outputs of the model enable system and chip designers to evaluate first-order trade-offs in energy efficiency, performance, and system cost. These fundamental data allow designers to make informed design and optimization trade-offs between asynchronous voltage-stacked architectures and the integrated circuits used therein. Analysis of this model shows that various voltage-stacked configurations, such as one with a 48 V supply using 100 rows and 11 columns, can be designed with less than 10% voltage variation per chip, mitigating the need for external voltage balancing.

Speed, Power and Area Optimized Monotonic Asynchronous Array Multipliers

Multiplication is a fundamental arithmetic operation in electronic processing units such as microprocessors and digital signal processors as it plays an important role in various computational tasks and applications. There exist many designs of synchronous multipliers in the literature. However, in the domain of Input–Output Mode (IOM) asynchronous design, there is relatively less published research on multipliers. Some existing works have considered quasi-delay-insensitive (QDI) asynchronous implementations of multipliers. However, the QDI asynchronous design paradigm, in general, is not area- and speed-efficient. This article presents an efficient alternative implementation of IOM asynchronous multipliers based on the concept of monotonic Boolean networks. The array multiplier architecture has been considered for demonstrating the usefulness of our proposition. The building blocks of the multiplier, such as the partial product generator, half adder, and full adder, were implemented monotonically. The popular dual-rail encoding scheme was considered for encoding the multiplier inputs and outputs, and four-phase return-to-zero handshaking (RZH) and return-to-one handshaking (ROH) were separately considered for communication. Compared to the best of the existing QDI asynchronous array multipliers, the proposed monotonic asynchronous array multiplier achieves the following reductions in design metrics: (i) a 40.1% (44.3%) reduction in cycle time (which is the asynchronous equivalent of synchronous clock timing), a 37.7% (37.7%) reduction in area, and a 4% (4.5%) reduction in power for 4 × 4 multiplication corresponding to RZH (ROH), and (ii) a 58.1% (60.2%) reduction in cycle time, a 45.2% (45.2%) reduction in area, and a 10.3% (11%) reduction in power for 8 × 8 multiplication corresponding to RZH (ROH). The multipliers were implemented using a 28 nm CMOS process technology.

Maximum likelihood estimators and Cramér–Rao bounds for the localization of an acoustical source with asynchronous arrays

The performances of source localization using a microphone array can be improved by repeating the experiment with different array placements, assuming that the source position remains constant. In this article, two types of theoretical results on this setting are presented. The Maximum Likelihood Estimator (MLE) is derived, and Cramér–Rao bounds are computed, both for a strict model, where the power of the source is constant, and a relaxed model where the power of the source is allowed to change. Cramér–Rao bounds show that the performances (in terms of mean squared error of the estimation of the position and power of the source) of asynchronous arrays for the estimation of the position are, in some settings, significantly degraded compared to synchronous arrays. A particular example of such a setting is the case of two parallel arrays around the source. In contrast, the performances of power estimation are, in most cases, close to the performances of synchronous arrays. The obtained MLEs are compared to the state of the art in asynchronous array source localization using simulations, showing that the MLE for the strict model outperforms the state of the art. Experimental results illustrate the theoretical and numerical findings.

Next-generation seismic model of the Australian crust from synchronous and asynchronous ambient noise imaging

The proliferation of seismic networks in Australia has laid the groundwork for high-resolution probing of the continental crust. Here we develop an updated 3D shear-velocity model using a large dataset containing nearly 30 years of seismic recordings from over 1600 stations. A recently-developed ambient noise imaging workflow enables improved data analysis by integrating asynchronous arrays across the continent. This model reveals fine-scale crustal structures at a lateral resolution of approximately 1-degree in most parts of the continent, highlighted by 1) shallow low velocities (<3.2 km/s) well correlated with the locations of known sedimentary basins, 2) consistently faster velocities beneath discovered mineral deposits, suggesting a whole-crustal control on the mineral deposition process, and 3) distinctive crustal layering and improved characterization of depth and sharpness of the crust-mantle transition. Our model sheds light on undercover mineral exploration and inspires future multi-disciplinary studies for a more comprehensive understanding of the mineral systems in Australia.

Three-dimensional location and attitude estimation using asynchronous acoustic beacons and microphone array

Three-dimensional location and attitude estimation using asynchronous acoustic beacons and microphone array

Fabrication Steps and Thermal Modeling of Three-Dimensional Asynchronous Field Programmable Gate Array (3D-AFPGA) With Through Silicon Via and Copper Pillar Bonding Approach

Abstract This work will specifically detail the development of a processing and fabrication route for a three-dimensional asynchronous field-programmable gate array (3D-AFPGA) design based on an extension of pre-existing two-dimensional-field-programmable gate array (2D-FPGA) tile designs. The periodic nature of FPGAs permits the use of an alternative approach, whereby the design entails splitting the FPGA design along tile borders and inserting through silicon vias (TSVs) at regular spatial intervals. This serves to enable true 3D performance (i.e., full 3D signal routing) while leaving most of the 2D circuit layouts intact. 3D signal buffers are inserted to handle communication between vertical and adjacent neighbors. For this approach, the density of vertical interconnections was shown to be determined by the size of the bond pads used for tier–tier communications and bonding. As a consequence, reducing bond pad dimensions from 25 μm to 15 μm, or 10 μm, bond pads are preferred to increase the connectivity between layers. A 3D-AFPGA mockup test structure was then proposed for completing development and exercising the 3D integration process flows. This mockup test structure consists of a three-tier demonstration vehicle consisting of a chip-to-wafer and a subsequent chip-to-chip bond. Besides, an alternate copper bonding approach using pillars was explored. Although the intended application is for the 3D integration process compatible with the 3D AFPGA design, the test structure was also designed to be generally applicable to various applications for 3D integration. Because of the importance of thermal management of 3D-AFPGA, it is important to predict the temperature distribution and avoid the maximum junction temperature. The numerical thermal modeling for predicting the equivalent thermal conductivity in every layer and the 3D temperature distribution in the 3D-AFPGA are developed and discussed as well.

Speed, energy and area optimized early output quasi-delay-insensitive array multipliers.

Multiplication is a widely used arithmetic operation that is frequently encountered in micro-processing and digital signal processing. Multiplication is implemented using a multiplier, and recently, QDI asynchronous array multipliers were presented in the literature utilizing delay-insensitive double-rail data encoding and four-phase return-to-zero (RTZ) handshaking and four-phase return-to-one (RTO) handshaking. In this context, this article makes two contributions: (i) the design of a new asynchronous partial product generator, and (ii) the design of a new asynchronous half adder. We analyze the usefulness of the proposed partial product generator and the proposed half adder to efficiently realize QDI array multipliers. When the new partial product generator and half adder are used along with our indicating full adder, significant reductions are achieved in the design metrics compared to the optimum QDI array multiplier reported in the literature. The cycle time is reduced by 17%, the area is reduced by 16.1%, the power is reduced by 15.3%, and the product of power and cycle time is reduced by 29.6% with respect to RTZ handshaking. On the other hand, the cycle time is reduced by 13%, the area is reduced by 16.1%, the power is reduced by 15.2%, and the product of power and cycle time is reduced by 26.1% with respect to RTO handshaking. Further, the RTO handshaking is found to be preferable to RTZ handshaking to achieve slightly improved optimizations in the design metrics. The QDI array multipliers were realized using a 32/28nm complementary metal oxide semiconductor (CMOS) process technology.

Empirical Green's Function Retrieval Using Ambient Noise Source‐Receiver Interferometry

AbstractEmpirical Green's function (EGF) retrieval commonly relies on cross‐correlating the long‐term ambient seismic wavefield that is simultaneously recorded at multiple stations. Recent studies have demonstrated observationally that cross‐correlating the coda of ambient noise cross‐correlation functions enables reconstruction of the EGFs, regardless of the operating time of the stations. In this study, we examine the feasibility of using the nondiffuse energy (i.e., surface waves) of the ambient noise cross‐correlation functions to retrieve EGFs between asynchronous stations. We show that source‐receiver interferometry (SRI), which is conventionally applied to reconstruct virtual seismograms between earthquake‐station pairs, provides an effective framework to retrieve EGFs between asynchronous stations. Our implementation of SRI exploits the nondiffuse wavefield rather than the scattered coda waves that may be contaminated by incoherent energy under nonideal (e.g., sparse, noisy, and short‐duration) network configurations. We demonstrate the robustness of SRI by retrieving asynchronous EGFs and performing seismic tomography between (1) nearby stations and (2) distant temporary arrays from southern Australia. The additional raypaths from asynchronous EGFs provide better illumination of small‐scale crustal structures beneath the regional network. In the larger‐scale example, involving two asynchronous arrays, SRI offers new constraints to the sparsely sampled region along the continental margin of southern Australia. The resulting velocity model agrees well with the independent structural constraints from each seismic array study and sedimentary thickness measurements. This study demonstrates that SRI is a promising tool for integrating seismic arrays operated at different times and can greatly benefit the efforts of improving data coverage and resolution in seismic imaging.

Early Output Quasi-Delay-Insensitive Array Multipliers

Multiplication is a widely used arithmetic operation in microprocessing and digital signal processing applications, and multiplication is realized using a multiplier. This article presents the quasi-delay-insensitive (QDI) early output versions of recently reported indicating asynchronous array multipliers. Delay-insensitive dual-rail encoding is used for data representation and processing, and 4-phase return-to-zero (RTZ) and return-to-one (RTO) handshake protocols are used for data communication. Many QDI array multipliers were realized using a 32/28 nm complementary metal oxide semiconductor (CMOS) technology. Compared to the optimum indicating array multiplier, the proposed optimum early output array multiplier achieves a 6.2% reduction in cycle time and a 7.4% reduction in power-cycle time product (PCTP) with respect to RTZ handshaking, and a 7.6% reduction in cycle time and an 8.8% reduction in PCTP with respect to RTO handshaking without an increase in the area. The simulation results also convey that the RTO handshaking is preferable to the RTZ handshaking for the optimum implementation of QDI array multipliers.

Acoustic localization method using time difference of arrival of asynchronous acoustic beacons and two-element microphone array

Acoustic localization method using time difference of arrival of asynchronous acoustic beacons and two-element microphone array

Combination of Asynchronous Array Pseudolites and GNSS for Outdoor Localization

Global navigation satellite systems (GNSS) are usually unable to provide location-based service (LBS) in urban canyons, thus the pseudolite positioning system has become an important way to enhance the availability and the accuracy of GNSS in such environments. However, the challenge of the traditional pseudolite positioning system is time synchronization, which requires complex hardware and visibility between pseudolites and reference receiver. Thus, the positioning in the urban environment becomes very difficult and complex. To solve this problem, a new asynchronous array pseudolites system is proposed in this paper. Multi-channel transmitters in array pseudolites system have an identical clock source and are based on an identical 1 pulse per second (1PPS) as well. The clock deviation of pseudolites' pseudorange can be eliminated by making the difference between array channels. The minimum positioning system consisting of one array pseudolite and three navigation satellites is used for positioning experiment in this paper. The results of the simulation verify the effectiveness of the minimum positioning system based on combined positioning. Compared with four navigation satellites, the horizontal positioning accuracy is improved slightly by exploiting the minimum positioning system.

マイクロホンアレイを搭載した複数ロボットによる自己位置・同期ずれ・音源位置・音源信号の推定

マイクロホンアレイを搭載した複数ロボットによる自己位置・同期ずれ・音源位置・音源信号の推定

Asynchronous cellular logic network as a co-processor for a general-purpose massively parallel array

This paper demonstrates an implementation of an asynchronous cellular processor array that facilitates binary trigger-wave propagations, extensively used in various image-processing algorithms. The circuit operates in a continuous-time mode, achieving high operational performance and low-power consumption. An integrated circuit with proof-of-concept array of 24×60 cells has been fabricated in a 0.35µm three-metal CMOS process and tested. Occupying only 16×8µm2 the binary wave-propagation cell is designed to be used as a co-processor in general-purpose processor-per-pixel arrays intended for focal-plane image processing. The results of global operations such as object reconstruction and hole filling are presented. Copyright © 2010 John Wiley & Sons, Ltd.

Architecture and Evaluation of an Asynchronous Array of Simple Processors

This paper presents the architecture of an asynchronous array of simple processors (AsAP), and evaluates its key architectural features as well as its performance and energy efficiency. The AsAP pr...

AsAP: An Asynchronous Array of Simple Processors

An array of simple programmable processors is implemented in 0.18 mum CMOS and contains 36 asynchronously clocked independent processors. Each processor occupies 0.66 and is fully functional at a clock rate of 520-540 MHz at 1.8 V and over 600 MHz at 2.0 V. Processors dissipate an average of 32 mW under typical conditions at 1.8 V and 475 MHz, and 2.4 mW at 0.9 V and 116 MHz while executing applications such as a JPEG encoder core and a fully compliant IEEE 802.11 a/g wireless LAN baseband transmitter.

Embedded Digital Signal Processing Systems

With continuing progress in VLSI and ASIC technologies, digital signal processing (DSP) algorithms have continued to find great use in increasingly wide application areas. DSP has gained popularity also in embedded systems although these systems set challenging constraints for implementations. Embedded systems contain limited resources, thus embedded DSP systems must balance tradeoffs between the requirements on computational power and computational resources. Energy efficiency has been important in batterypowered devices, but nowadays also the limited heat dissipation in small devices calls for low-power consumption. Successful implementation of DSP applications in embedded systems requires tailoring, which in turn sets challenges for design methodologies. For this special issue, we received 14 submissions and a collection of seven papers was finally accepted. The special issue is opened by “Observations on power-efficiency trends in mobile communication devices,” where the authors O. Silven and K. Jyrkka analyze the power consumption in the current mobile communication devices. Several bottlenecks in the current implementation style have been identified, thus the paper provides a good motivation for the following papers. In “The Sandbridge SB3011 platform,” the authors John Glossner et al. describe a system-on-a-chip (SoC) multiprocessor targeted as a software-defined radio platform. The platform provides solutions to the challenges in future mobile devices given in the previous paper. “A shared memory module for asynchronous arrays of processors” authored byMichael J. Meeuwsen et al. considers also chip multiprocessors. The presented shared memory module can be used for interprocess communication or to increase application performance by parallelizing computation. In “Implementing a WLAN video terminal using UML and fully automated design flow” by Petri Kukkala et al., an automated design flow for multiprocessor SoC is presented. The flow is based on UML descriptions and the authors demonstrate their design flow with a design case. Programming of chip multiprocessor platforms is considered in “pn: a tool for improved derivation of process networks” by Sven Verdoolaege et al. The paper discusses conversion of sequential programs to process networks allowing optimization of communication channels and buffers. In “A SystemC-based design methodology for digital signal processing systems,” the authors Christian Haubelt et al. describe a design flow for SoC designs containing automatic design space exploration, performance evaluation, and automatic platform-based system generation. The design flow is based on SystemC descriptions and the presented tools can automatically detect the underlying model of computation. Application-specific implementations are often used to speedup certain DSP tasks in embedded systems. In “Priority-based heading one detector in H.264/AVC decoding,” the authors Ke Xu et al. consider such implementations to speed up video decoding applications. The authors present a low-power decoder implementation for context-adaptive variable length coding defined in H.264 standard.

A Shared Memory Module for Asynchronous Arrays of Processors

A Shared Memory Module for Asynchronous Arrays of Processors

A Shared Memory Module for Asynchronous Arrays of Processors

A shared memory module connecting multiple independently clocked processors is presented. The memory module itself is independently clocked, supports hardware address generation, mutual exclusion, ...

Maximizing the throughput of large ad hoc wireless networks

Ad hoc wireless networks can be quickly deployed to provide wireless communication services in areas without pre-established infrastructure of base stations. Since delivering signals between sources and destinations is a primary function of ad hoc networks, the design and analysis of ad hoc networks are also a task of signal processing. In this paper, we review some of the major results on maximum throughput of ad hoc networks. Both single-hop ad hoc networks and multi-hop ad hoc networks are considered. In particular, we show examples of how to maximize the throughput of a large ad hoc network through a closed-loop analysis of two medium access control (MAC) schemes: synchronous array method (SAM) and asynchronous array method (AAM). Both omni-directional antennas and directional antennas are examined. This study illustrates an importance of the interplays between signal processing, information theory and networking protocols.