Abstract
Multiplication is a widely used arithmetic operation in microprocessing and digital signal processing applications, and multiplication is realized using a multiplier. This article presents the quasi-delay-insensitive (QDI) early output versions of recently reported indicating asynchronous array multipliers. Delay-insensitive dual-rail encoding is used for data representation and processing, and 4-phase return-to-zero (RTZ) and return-to-one (RTO) handshake protocols are used for data communication. Many QDI array multipliers were realized using a 32/28 nm complementary metal oxide semiconductor (CMOS) technology. Compared to the optimum indicating array multiplier, the proposed optimum early output array multiplier achieves a 6.2% reduction in cycle time and a 7.4% reduction in power-cycle time product (PCTP) with respect to RTZ handshaking, and a 7.6% reduction in cycle time and an 8.8% reduction in PCTP with respect to RTO handshaking without an increase in the area. The simulation results also convey that the RTO handshaking is preferable to the RTZ handshaking for the optimum implementation of QDI array multipliers.
Highlights
Multiplication is an important arithmetic operation widely used in microprocessing and digital signal processing [1,2]
This article discusses many quasi-delay-insensitive (QDI) implementations of the array multiplier and contributes by presenting the QDI early output versions of recently reported indicating array multipliers [3], which leads to simultaneous decreases in cycle time, power-cycle time product (PCTP), and silicon area
0), which may not be acknowledged by the array multiplier, will fork assumption is imposed on all the primary inputs and no wire orphan would occur
Summary
Multiplication is an important arithmetic operation widely used in microprocessing and digital signal processing [1,2]. We consider many early output QDI designs of the array multiplier and compare them with recently proposed weak-indication array multipliers [3]. Compared to [3], which presents indicating QDI array multipliers, the proposed early output QDI array multipliers achieve reductions in cycle time and power-cycle time product (PCTP) without increasing the area and without compromising on the robustness.
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