Asymmetrical Multilevel Inverter Topology Research Articles

A new single modulating and single carrier signal based control technique for symmetrical and asymmetrical multilevel inverter topology

Abstract In literature, to generate gate pulses for any inverter topology, most of the authors are using a single modulating signal with (level-1) or (level-1)/2 carrier-based pulse width modulation (PWM) techniques and single carrier (SC) signal with (level-1)/2 modulating signal based PWM techniques. Then, while going to higher-level inverter topologies, the complexity of the PWM control approach in both cases can increase. To reduce the control complexity, few authors have reported a single modulating signal with single carrier-based PWM techniques. However, these techniques need more mathematical equations and if-else loops. This article proposes a new single-modulating and single-carrier signal-based generalized PWM control approach using floor function (FF). This technique has been verified by considering one of the single-phase conventional symmetrical and asymmetrical multilevel inverter (MLI) topologies. Generally, FF rounds the value to the nearest integer towards the negative infinity. The proposed PWM control implementation process is very simple and suitable for both high switching frequency (HSF) and low switching frequency (LSF) operations. The proposed control technique (PCT) has been experimentally verified with different steady-state and transient-state studies of results under standalone operation.

Computerised Gate Firing Control for 17-Level MLI using Staircase PWM

A basic 7-level MLI topology is developed and the same is extended to the 9-level then further increased to 17-levels. The developed structure minimizes the component’s count and size to draw out the system economy. Despite the various advantages of MLIs, efficiency and reliability play a major role since the usage of components is higher for getting a low Total Harmonics Distortion (THD) value. This becomes a major challenge incorporated in boosting the efficiency without affecting the THD value. Various parametric observations are done and realized for the designed 9-level and 17-level MLI, being the Total Standing Voltage (TSV), efficiency, cost function per level count, and power loss. The respective parameters are compared with several existing and modern circuits and found to be effective in their performance. A novel single-phase 17-level asymmetrical Multi-Level Inverter (MLI) topology is developed to reduce the number of overall components. The developed topology generates 17-levels by using unequal DC sources. The developed MLI is proved under various tests conducted experimentally for the various loads like resistive, inductive, and combinational loads. A detailed comparison is done on several factors and represented graphically represented. Further, the proposed design provides a less TSV value is 6 Vdc, efficiency is 94.21% and cost factor per level CF/L value for both values of α is 2.01 and 2.05 and devices count with a low THD value 41.4% with respectively.

Asymmetrical 21‐level inverter topology with minimum variety of dc sources and reduced component counts

SummaryThis paper proposes an asymmetrical multilevel inverter (MLI) topology. The inverter utilizes 12 switches, four dc sources, and two diodes to generate 21 levels. The main advantage of the converter is that it can generate 21 levels with a reduced number of switches, dc sources, and a variety of sources compared with other MLI topologies. It only utilizes two varieties of dc sources to generate the 21 levels. In addition, the topology can be easily extended to the n‐level topology. The efficiency of the proposed MLI is determined by considering switching and conduction losses in the switches using PLECS, and simulation is carried out in MATLAB/SIMULINK. The nearest level control (NLC) technique is deployed to generate the switching signals. The inverter has 3.91% THD in the output voltage without filtering. The maximum voltage stress to withstand is found to be 0.7 per unit. Economic analysis of the topology is done to determine its feasibility, and the cost factor is found to be 1.53 per level, making it an economically viable option. To validate the performance of the proposed converter, an experimental prototype is developed in the laboratory and tested under different loading conditions. The comparison of the proposed topology with other MLI structures is based on the number of voltage levels, dc sources, variety of sources, driver circuits, and the TSV. Results obtained show that the proposed topology outperformed other topologies on many parameters.

Asymmetrical eleven‐level inverter topology with reduced power semiconductor switches, total standing voltage and cost factor

Voltage source multilevel inverters (MLI) is widely utilized in medium and high-power applications due to their advantages. Here, an 11-level, asymmetrical multilevel inverter topology is proposed. The topology utilizes four unidirectional switches, three bidirectional switches along with two dc sources. The proposed configuration of switches and the concept of the dc-link capacitor is utilized to generate eleven level output voltage. The reduced number of components such as power switches and DC sources, lower control complexity due to capacitors' self-balancing nature, and low total standing voltage (TSV) are the critical features of the proposed topology. Moreover, a reliability assessment of the topology shows that the topology has a high mean time to fault (MTTF), which makes it robust and reliable. Matlab/Simulink environment is used to develop a simulation model of the proposed topology, while PLECS is used for the thermal modelling and analysis of the converter. A prototype is developed and tested in the laboratory to validate the performance for different loading conditions. The proposed topology can be cascaded to produce the ‘n’ number of levels. The critical comparison of the proposed topology shows that the proposed circuit has advantages over other compared topologies.

Asymmetric Multilevel Inverter Topology and Its Fault Management Strategy for High-Reliability Applications

As the applications of power electronic converters increase across multiple domains, so do the associated challenges. With multilevel inverters (MLIs) being one of the key technologies used in renewable systems and electrification, their reliability and fault ride-through capabilities are highly desirable. While using a large number of semiconductor components that are the leading cause of failures in power electronics systems, fault tolerance against switch open-circuit faults is necessary, especially in remote applications with substantial maintenance penalties or safety-critical operation. In this paper, a fault-tolerant asymmetric reduced device count multilevel inverter topology producing an 11-level output under healthy conditions and capable of operating after open-circuit fault in any switch is presented. Nearest-level control (NLC) based Pulse width modulation is implemented and is updated post-fault to continue operation at an acceptable power quality. Reliability analysis of the structure is carried out to assess the benefits of fault tolerance. The topology is compared with various fault-tolerant topologies discussed in the recent literature. Moreover, an artificial intelligence (AI)-based fault detection method is proposed as a machine learning classification problem using decision trees. The fault detection method is successful in detecting fault location with low computational requirements and desirable accuracy.

A Novel Cascaded Symmetric and Asymmetric Multilevel Inverter Topology with Minimum Number of Power Electronics Components

A Novel Cascaded Symmetric and Asymmetric Multilevel Inverter Topology with Minimum Number of Power Electronics Components

A Single-Phase Reduced Component Count Asymmetrical Multilevel Inverter Topology

Multilevel inverters (MLIs) have gained wide attention in industry and academia to provide higher voltage levels with lower harmonics, power losses, and cost. This study proposes a new asymmetrical MLI topology with reduced component count (RCC). The proposed topology can be extended in a three-phase structure and both modular and cascaded configurations to generate the required number of voltage levels for high-voltage applications. To minimize the power losses and the voltage stress on the switches, this configuration has the potential to produce negative polarity without an H-bridge configuration, thereby the active switches are reduced to only three switches in the conduction path. Due to the possibility of applying different switching patterns, this article proposes a new solution by employing particle swarm optimization (PSO) algorithm to determine the optimized dc sources’ magnitude. To improve the voltage quality and minimize the total harmonic distortion (THD), the optimal switching angle (OSA) modulation technique is applied to determine the optimum switching angles by the PSO algorithm. Moreover, the proposed topology’s effectiveness compared to the conventional cascaded H-bridge (CHB) MLI with 15-levels is illustrated by providing comparative results that express fewer power losses. Finally, the proposed topology’s feasibility and its optimization approach are validated by a single-phase prototype utilizing 15- and 25-levels.

Investigation and Reliability Analysis of Fifteen-level Asymmetrical Multilevel Inverter Topology using Nearest Level Control Technique with low Component Count

Background:: In multilevel inverters (MLI) as the number of level increases, there is a proportionate increase in the count of the semiconductor devices that are employed. Methods:: An asymmetrical multilevel inverter topology using a bidirectional switch is presented which employs lesser number of power electronic devices to produce fifteen levels at the output voltage. Nearest Level modulation (NLM) technique is used to generate the switching pulses and reliability analysis is performed using Markov reliability methodology. The operating principle of the proposed MLI and its performance abilities is verified through MATLAB/Simulink and a prototype is developed to provide the experimental results. Results:: Total Harmonic Distortion (THD) is computed for proposed MLI for different types of loads in simulation environment as well as in the developed hardware prototype. The fifteen level is achieved by using only 9 switches and 3 DC sources in comparison to the 28 switches and 6 DC sources required by the traditional cascaded H-bridge inverter. Conclusion:: The simulation and hardware results confirm the suitability of the proposed fifteen level MLI as the total component count and the requirement of DC sources reduces considerably.

Asymmetrical multilevel inverter topology with low total standing voltage and reduced switches count

SummaryThis paper presented an improved asymmetrical multilevel inverter module with reduced switches count. The basic module is capable of producing 15 level outputs with four dc sources and 10 switches. The proposed topology has an inherent ability to generate negative voltage levels, made it possible to utilize lower rating switches, and has lower total standing voltage. To have more number of levels, a series‐connected cascade extension of the module has been done. The three different algorithms for selecting the magnitude of dc sources are proposed. The generalized relations for different parameters are based on the number of added basic units and the number of presented levels for each source selection algorithm. Nearest level control (NLC) is used as the modulation technique. A comparative study shows that the developed topology outperformed other selected existing topologies on many parameters. The performance of the module is evaluated through detailed simulation and power loss analysis. Accuracy of the obtained simulation results is validated through proper experimental testing of the circuit in the laboratory.

Symmetrical and Asymmetrical Reduced Device Multilevel Inverter Topology

This article presents a single-phase symmetrical and asymmetrical multilevel inverter (MLI) topology. The presented topology can generate 9-level output voltage in a symmetrical configuration and 13- and 17-level output voltage in asymmetrical configuration with a single cell. The number of output levels can be improved further by increasing either the number of cells or switches in a single cell. The presented topology contains the least number of dc sources, semiconductor switches, capacitors, and diodes compared with classical and recently proposed topologies. Reduction in component count decreases the size, complexity, and cost of the overall converter. A detailed comparison has been done of the presented topology with the recently proposed topologies in terms of dc sources, semiconductor switches, capacitor, and total blocking voltage. Finally, to validate the presented concept, the prototype of the presented 9-, 13-, and 17-level MLI topologies has been tested in the laboratory for different switching frequencies, different modulation indexes, sudden load changes, and nonlinear load.

Marxiplier: An Innovative Marx-Based Single-Source Multilevel Inverter With Voltage Multiplying Capability

This article proposes a novel single-source high step-up asymmetrical multilevel inverter (MLI) topology based on Marx generator configuration with voltage multiplying capability. The operating principles of the proposed converter (which is named Marxiplier) are completely different from the MLIs presented in the literature. Proposed converter uses a low-voltage dc source with high-frequency inverter (low-voltage ac input) and charges a series of capacitors multiple times of input voltage. These capacitors which work as asymmetrical sources can generate a high-amplitude ac output voltage with high number of levels. Another important aspect of this converter is producing negative levels in the output voltage without using a high-voltage full-bridge inverter and reducing the number of the components. MATLAB simulations and a laboratory test results of a 21-level prototype are employed in order to verify the proposed converter operation.

A new cascaded asymmetrical multilevel inverter based on switched dc voltage sources

Multilevel inverters are now becoming an important element for medium-voltage high-power applications. A low switch count multilevel inverters are currently attracting more attention due to its high efficiency, low cost, and easy control. This paper proposes a new single-phase cascade asymmetrical multilevel inverter topology based on switched dc voltage sources which is capable of achieving a higher number of output levels using fewer number of switches, driver circuits, and dc voltage sources. Other advantages include the inherent generation of negative voltage levels and lower voltage stress across the switches. Three different approaches in selecting the magnitude of the sources for the cascade connection has been included to produce a higher number of voltage levels. Furthermore, the power loss and fault-tolerant analysis of the proposed basic module has also been discussed. To set the benchmark of the proposed multilevel inverter structure, a comparison with several recently proposed topologies is carried out. The comparison has been carried out for the basic module, generalized structure, and cascade connection. The proposed topology gave improved parameters for all three categories. Fundamental switching frequency modulation technique is used to achieve high-quality output voltage waveforms with lower harmonic contents and reduced switching losses. Finally, the operation and performance of the proposed basic module and its cascade connection for two modules are presented together with experimental results in several steady-state and dynamic operating conditions.

Design and Implementation of 31-Level Asymmetrical Inverter With Reduced Components

This paper presents a novel topology for the single-phase 31-level asymmetrical multilevel inverter accomplished with reduced components count. The proposed topology generates maximum 31-level output voltage with asymmetric DC sources with an H-bridge. The fundamental 13-level multilevel inverter (MLI) topology is realized, and further, the topology is developed for 31-level can be used for renewable energy applications. This reduces the overall components count, cost and size of the system. Rather than the many advantages of MLIs, reliability issues play a significant role due to higher components count to reduce THD. This is a vital challenge for the researchers to increase the reliability with less THD. Several parameters are analyzed for both fundamental 13-level and developed 31-level MLIs such as total standing voltage (TSV), cost function (CF) and power loss. The inverter is tested experimentally with various combinational loads and under dynamic load variations with sudden load disturbances. Total standing voltage with the cost function for the proposed MLI is compared with various topologies published recently and is cost-effective. A detailed comparison of several parameters with graphical representation is made. Less TSV and components requirement is observed for the proposed MLI. The obtained total harmonic distortion (THD) is under IEEE standards. The topology is simulated in MATLAB/Simulink and verified experimentally with a hardware prototype under various conditions.

Asymmetrical 17-Level Inverter Topology With Reduced Total Standing Voltage and Device Count

Voltage source Multilevel Inverters (MLIs) are vital components for medium voltage and high-power applications due to their advantages like modularity and better power quality. However, the number of components used is significant. In this paper, an improved asymmetrical multilevel inverter topology is proposed producing 17-levels output voltage utilizing two dc sources. The circuit is developed to reduce the number of isolated dc-sources used without reducing output levels. The circuit utilizes six two-quadrant switches, three four-quadrant switches and four capacitors. The capacitors are self-balancing and do not require extra attention, i.e. the control system is simple for the proposed MLI. Detailed analysis of the topology under linear and non-linear loading conditions is carried out. Comparison with other similar topologies shows that the proposed topology is superior in device count, power quality, Total Standing Voltage (TSV), and cost factor. The performance of the topology is validated for different load conditions through MATLAB/Simulink environment and the prototype developed in the laboratory. Furthermore, thermal analysis of the circuit is done, and the losses are calculated via PLECS software. The topology offers a total harmonic distortion (THD) of 4.79% in the output voltage, with all the lower order harmonics being less than 5% complying with the IEEE standards.

Enhancement of Power Quality for 15 Level Inverter using Phase Disposition-PWM Technique

With consideration of use of solar, wind and other renewable energy source for industrial applications like electric vehicle drive, train traction and FACTS integration, which demand voltage levels in the range of kilo volts with high power quality, to achieve this high voltage level and high quality of power, a cascaded H-bridge multilevel inverter based topology capable of operating with low harmonic distortion is proposed in the paper. In order to attain low total harmonic distortion (THD), use of phase disposition-PWM technique is proposed in the paper. Giving due attention to both switch count and low THD, the output voltage levels of the multi-level inverter are set at 15 levels. Due to half wave symmetry the even order harmonics for proposed system become zero and the lower order harmonics reduces which is shown in tabular from. Due to reduced switch count and low THD the overall system become more efficient and effective. The effectiveness of the proposed control strategy has been verified using MATLAB simulations. Simulation is done for both symmetrical as well as asymmetrical multilevel inverter topology. It is observed that quality of the output voltage waveforms of the multi-level inverter (MLI) is as per the IEEE std 519 specifications. For symmetrical reduced switch fifteen level inverter the THD is 4.42% and for asymmetrical topology THD is 4.59% for the output voltage waveform.

An improved asymmetrical multilevel inverter topology with reduced semiconductor device count

An improved asymmetrical multilevel inverter topology with reduced semiconductor device count

Performance Analysis of a Half Bridge Cell Based Asymmetrical Multilevel Inverter Topology with Minimum Components

Background: In Multilevel Inverters (MLI) as the number of level increases, there is a proportionate increase in the count of the semiconductor devices that are employed. Methods: This paper deals with an asymmetrical cascaded H-bridge inverter topology with half bridge cells to produce seven level output voltage waveform. Nearest Level Control (NLM) technique is used to produce the switching pulses. The operating principle of the proposed MLI and its performance abilities is verified through MATLAB/Simulink and a prototype is developed to provide the experimental results. Results: Total Harmonic Distortion (THD) is computed for proposed MLI for different types of loads in simulation environment as well as in the developed hardware prototype. Comparison between the proposed MLI and recent topologies demonstrates the advantageous features. Conclusion: The simulation and hardware results confirm the suitability of the proposed seven level MLI as the total component count, and the requirement of DC sources reduces considerably.

A novel single-phase PWM asymmetrical multilevel inverter with number of semiconductor switches reduction

In this paper, a new asymmetrical multilevel inverter topology (MLI) is proposed with the objectives of using decreased number of semiconductor switches, dc voltage sources, gate driver circuits and dc links. The structure of presented MLI is very simple and modular. The fundamental module of this structure consists of nine semiconductor switches (eight unidirectional and one bidirectional) and four asymmetrical configured DC sources (ratio of 1:2), which can generate 13-level output voltage. To validate the design, a Matlab-Simulink based model is developed. For this paper, a Sinusoidal Pulse Width Modulation (SPWM) is deployed as the switching strategy of the proposed MLI. The circuit model is simulated under pure resistive and inductive loads. It will be shown that the circuit performs well under both loads. Comparison with traditional MLIs and other recently introduced MLIs will be conducted to show the superiority of the proposed MLI in terms of reduced number of devices and lower voltage stress across the switches.

Multilevel inverter with MPWM-LFT switching strategy for voltage THD minimization

<span>This paper presents a proposed modified pulse width modulation – low frequency triangular (MPWM-LFT) switching strategy for minimization of voltage THD with implementation of asymmetric multilevel inverter (AMLI) topology on the reduced number of switching devices (RNSD) circuit structure. Principally, MPWM-LFT able to produce optimum angle of the output voltage level in order to minimize total harmonic distortion (THD). In this study, 5-level reduced number of switching devices circuit structure is selected as a circuit configuration for asymmetric (7-level structure) multilevel inverter. For switching strategy, MPWM used low switching frequency in producing signal and needs higher output voltage levels to achieve low total harmonic distortion. In contrast, sinusoidal pulse width modulation used high switching frequency in order to minimize total harmonic distortion. By optimizing angle at the output voltage using MPWM-LFT switching strategy, the voltage THD is lower as compared to MPWM and SPWM switching strategies. MPWM-LFT switching strategy obtains 11.6% of voltage THD for the 7-level asymmetric topology as compared to MPWM and SPWM switching strategies with the voltage THD are 21.5% and 17.5% respectively from the experimental works.</span>

Implementation of a Solar based Seven Level Asymmetrical Multilevel Inverter Topology with reduced device count

A multilevel inverter with half bridge cells and seven switches is implemented for Solar PV based applications. The photovoltaic panels are employed to replace the DC sources and maximum power is ensured by employing a boost converter andPerturb and Observe(P&O) algorithm. The generation of switching pulses is carried by usingNearest Level Control(NLC) technique.The operating principle of the proposed multilevel inverter(MLI) is verified by utilizing different loads and the experimental results are obtained through prototype testing.