Abstract
This paper presents a novel topology for the single-phase 31-level asymmetrical multilevel inverter accomplished with reduced components count. The proposed topology generates maximum 31-level output voltage with asymmetric DC sources with an H-bridge. The fundamental 13-level multilevel inverter (MLI) topology is realized, and further, the topology is developed for 31-level can be used for renewable energy applications. This reduces the overall components count, cost and size of the system. Rather than the many advantages of MLIs, reliability issues play a significant role due to higher components count to reduce THD. This is a vital challenge for the researchers to increase the reliability with less THD. Several parameters are analyzed for both fundamental 13-level and developed 31-level MLIs such as total standing voltage (TSV), cost function (CF) and power loss. The inverter is tested experimentally with various combinational loads and under dynamic load variations with sudden load disturbances. Total standing voltage with the cost function for the proposed MLI is compared with various topologies published recently and is cost-effective. A detailed comparison of several parameters with graphical representation is made. Less TSV and components requirement is observed for the proposed MLI. The obtained total harmonic distortion (THD) is under IEEE standards. The topology is simulated in MATLAB/Simulink and verified experimentally with a hardware prototype under various conditions.
Highlights
In the recent past, multilevel inverters gain attention due to their high power operation capability and several benefits like lower harmonics, high power quality, and lower switching losses with improved electromagnetic interference [1], [2]
SIMULATION AND EXPERIMENTAL RESULTS OF 13-LEVEL multilevel inverter (MLI) Presented 13-level MLI topology is simulated in MATLAB/Simulink, switching pulses are generated at 2 kHz switching frequency compared with 50Hz reference frequency, the topology is tested for 100 resistive load, maximum peak voltage 400V is attained by giving input DC sources Vdc = V1 = 66.6V, V2 = 133.3V, and V3 = 200V respectively
The waveforms are observed in digital storage oscilloscope (DSO), experimental prototype results with R-Load under steady-state output voltage V0 = 400V equal to 282.84 Vrms, load current I0 = 4A equal to 2.82A Irms are represented in Fig. 9(a) & (b) respectively
Summary
Multilevel inverters gain attention due to their high power operation capability and several benefits like lower harmonics, high power quality, and lower switching losses with improved electromagnetic interference [1], [2]. A transistor clamped H-bridge MLI topology is presented in [38] provides several output levels, where the higher voltage and power ratings are achieved without expanding the components’ rating This type has the benefits of less switching losses with under high switching frequencies with high efficiency [39]–[44] controlled by a carrier-based PWM technique. A positive peak voltage level switches S1, S3, S5,S8, S9, and S13 are in conduction stage, the path of load current Io through V1-S8S1-S14-V2-V4-S13-S5-L-S3-S9-V3-V1, all four sources V1, V2, V3, and V4 supplies the circuit produce +15Vdc output level. The negative peak voltage level is occurring at switches S2, S4, S6,S8, S9, S13, and S14 are in conduction stage; the path of load current Io through V1-S8-S2-L-S6-S14-V2-V4-S13-S4-S9-V3-V1, all four sources V1, V2, V3, and V4 supplies the circuit produce −15Vdc output level, likewise remaining negative level are achieved by controlling the switches and DC sources.
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