Asymmetric Doping Profile Research Articles

Asymmetric doping induced nonlinear electron mobility in double V-shaped quantum well based FET structure under external electric field

The effect of asymmetric doping profile on the electron mobility μ is studied in a Field Effect Transistor (FET) structure based on Al x Ga 1−x As double V-shaped quantum well (D-VQW) in presence of an external electric field F. We introduce asymmetry in the structure by considering different doping concentrations in the side barriers along the substrate and surface. The resultant asymmetric potential is varied as a function of F. Accordingly the energy levels E l and wave functions ξ l within the coupled structure alter. By varying F suitably the resonance of subband states can be realized between the wells. Around the point of resonance, ξ l rearranges significantly. The change in ξ l influences the screened scattering potentials through intersubband effects leading to nonlinear μ. We consider ionized impurity (Imp-) scattering and alloy disorder (Al-) scattering for the D-VQW structure and show that under double subband occupancy, μ has an oscillatory behavior, basically due to Imp-scattering. The oscillatory μ enhances by increasing the well width and central barrier width and also by decreasing the height of the V-shaped well. Our results of nonlinear electron mobility can be employed to tune the transistor performance with gate electric field by adopting an optimized set of structure parameters.

An Asymmetrically Doped Vertical Si Biristor With Sub-1-V Operation

Vertical biristors are small footprint ( 4F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) floating base bipolar junction transistors (BJTs) proposed for high-speed volatile memory applications. One key challenge is (i) the high latch-up voltage with Si-based biristors because of the high threshold of impact ionization (II) in Si. In this article, an epitaxial n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> /i/δp <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> /i/n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -based vertical biristor is proposed with an asymmetric doping profile that enables sub-bandgap II only in the negative polarity. First, in the negative polarity, a latch-up voltage as low as 0.5 V due to sub-bandgap II is demonstrated. Faster programming with higher bias is observed. Second, erase is demonstrated in the positive bias, where II is insignificant. Overall, a large read window ( Δ I=0.01 mA) with a low variability ( σ/μ in ΔI) for cycle-to-cycle (C2C <; 1%) and device-to-device (D2D <; 5%). Retention in excess of 1 μs is observed, taking into account C2C and D2D variations. A high endurance (> 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> cycles) is also observed. Therefore, asymmetrically doped vertical biristor is promising for very low voltage high speed memory application compared to dynamic random access memory (DRAM).

Improved two-dimensional electron mobility in asymmetric barrier delta-doped GaAs/AlGaAs modulation-doped field-effect transistor structures

We study the enhancement of electron mobility μ in barrier delta-doped GaAs/AlGaAs quantum-well-based modulation-doped field-effect transistor (MODFET) structures. We asymmetrically vary the doping concentrations Nd1 and Nd2 in the barriers on the substrate and surface sides, respectively, to obtain a nonlinear enhancement of μ as a function of the well width w through multi-subband effects. We show that an increase in doping concentration increases the surface electron density Ns, which in turn enhances μ. Interchanging Nd1 and Nd2 leads to no change in Ns but rather, an enhancement of μ as a function of w for Nd2 > Nd1 owing to asymmetric variation of subband wave functions, thereby implying a higher channel conductivity in a surface-doped structure than in an inverted doped structure. By keeping (Nd1 + Nd2) unchanged, the conductivity of a single-channel MODFET, Nd1 (Nd2) ≠ 0 and Nd2 (Nd1) = 0, can be enhanced by considering a MODFET based on an asymmetrically doped (Nd1 ≠ Nd2 ≠ 0) quantum well structure. We show that the highest Ns and μ product for these structures occurs almost before the onset of the occupation of the second subband. Our analysis of the effect of asymmetric doping profiles on channel conductivity can be utilized for the performance improvement of MODFET-like devices.

Self-consistent quantum drift-diffusion model for multiple quantum well IMPATT diodes

In this paper, the authors have presented a self-consistent quantum drift-diffusion model for multiple quantum well (MQW) impact avalanche transit time (IMPATT) diodes. The bound states in MQWs have been taken into account by self-consistent solutions of the coupled classical drift-diffusion (CLDD) equations and time-independent Schrodinger equations associated with both the conduction and valence bands. The static and high-frequency properties of MQW DDR IMPATTs based on Si$$\sim $$~3C-SiC material system designed to operate near 94-GHz atmospheric window have been studied by means of the above-mentioned self-consistent solutions of coupled CLDD equations and Schrodinger equations followed by a well-established double-iterative field maximum computational technique. A symmetric and two complementary asymmetric doping profiles for the proposed structures have been taken into account for the present study. The RF power outputs of Si$$\sim $$~3C-SiC MQW DDR IMPATTs near 94 GHz obtained from the simulation are compared with the experimentally obtained power outputs of flat DDR IMPATT diodes based on Si, GaAs, and InP at the same frequency band. It is observed that Si$$\sim $$~3C-SiC MQW DDR IMPATTs are capable of delivering significantly higher RF power compared with IMPATTs based on the above-mentioned materials especially when the doping concentrations of 3C-SiC layers are kept higher than those of the Si layers.

Effect of Drain Doping Profile on Double-Gate Tunnel Field-Effect Transistor and its Influence on Device RF Performance

In this paper, we have investigated the effect of drain doping profile on a double-gate tunnel field-effect transistor (DG-TFET) and its radio-frequency (RF) performances. Lateral asymmetric drain doping profile suppresses the ambipolar behavior, improves OFF-state current, reduces the gate-drain capacitance, and improves the RF performance. Further, placing the high-density layer in the channel near the source-channel junction, a reduction in the width of depletion region, improvement in ON-state current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ), and subthreshold slope are analyzed for this asymmetric drain doping. However, it also improves many RF figures of merit for the DG-TFET. Furthermore, lateral asymmetric doping effects on RF performances are also checked for the various channel length. Therefore, this paper would be beneficial for a new generation of RF circuits and systems in a broad range of applications and operating frequencies covering RF spectrum. So, the RF figures of merit for the DG-TFET are analyzed in terms of transconductance (g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ), unit-gain cutoff frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ), maximum frequency of oscillation (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ), and gain bandwidth product. For this, the RF figures of merit have been extracted from the V-parameter matrix generated by performing the small-signal ac analysis. Technology computer-aided design simulations have been performed by 2-D ATLAS, Silvaco International, Santa Clara, CA, USA.

Asymmetric channel doping profile and temperature reduction influence on the performance of current mirrors implemented with FD SOI nMOSFETs

In this work a comparison between the performance of current mirrors implemented with uniformly doped and graded-channel (GC) transistors operating down to low temperature (150K) is presented. This analysis has been carried out through experimental measurements of Common-source, Cascode and Wilson current mirrors architectures. The advantages of the use of graded-channel transistors for implementation of current mirrors in comparison to standard ones is discussed, focusing on the increase of output swing and output resistance. In all architectures some performance degradation has been observed with the temperature reduction, although current mirrors with GC transistors still present better performance than those implemented with standard SOI transistors. Two-dimensional numerical simulations were performed in order to further investigate the behavior of graded-channel current mirrors, looking at the bias condition of each transistor in the current mirror architectures. The obtained results indicate that good performance, compared to that of GC current mirrors, may be obtained by combining both standard and graded-channel transistors, rather than using the same channel engineering for all devices in the circuit.

Highly reproducible tunnel currents in MBE-grown semiconductor multilayers

Tunnel currents through semiconductor tunnel barriers have proved very difficult to control to the extent that device-to-device variability and wafer-to-wafer irreproducibility have prevented electronic devices based on tunnelling from ever going into production. With reference to a single tunnel barrier of AlAs in a GaAs multilayer structure with an asymmetric doping profile, it is shown that, with careful attention to detail, diodes from equivalent sites on three separate wafers can be produced whose average current in forward bias is within 1 % while the total in-wafer standard deviation of current at the same fixed bias (0.5 V) is 6 %, dominated by a systematic cross-wafer variation that is described. This level of reproducibility now enables these devices to be used in pick-and-place systems for the manufacture of low-cost hybrid integrated microwave circuits.

Simulation of asymmetric doped high performance silicon on insulator metal oxide semiconductor field effect transistors for very large scale integrated complementary metal oxide semiconductor technologies

Asymmetric halo and extension implantations are examined by simulation for their usability in 45 and 32 nm technology high performance silicon on insulator metal oxide semiconductor field effect transistors (SOI-MOSFETs). Tilted halo and extension implantations from the source side show higher saturation currents and lower drain overlap and junction capacitances, which improve the intrinsic MOSFET power delay product. Furthermore the asymmetric doping profile leads to an inverter chain speed benefit. The stronger short channel effect, present in these devices, can be reduced by a low dose drain side halo implantation simultaneously maintaining a transistor performance improvement from asymmetric doping. This optimized transistor design is successfully transferred from the 45 into the 32 nm technology.

An extended drain current conductance extraction method and its application to DRAM support and array devices

In this paper an extended drain-current conductance method is introduced, which can be used for extraction of separated drain and source resistors, forward and reversed modes carrier mobilities and effective channel length of MOSFET. The new single device extraction method is successfully applied to logic devices with symmetric doping profiles and DRAM array devices with highly asymmetric doping profiles. Furthermore a new physical definition is introduced for effective channel length which provides a better understanding of the device.

Scaling considerations for sub-90 nm split-gate flash memory cells

A systematic methodology is presented to scale split-gate (SG) flash memory cells in the sub-90 nm regime within the presently known scaling constraints of flash memory. The numerical device simulation results show that the high performance sub-90 nm NOR-type SG cells can be achieved by a suitable channel and source-drain engineering. An asymmetric channel doping profile along with ultra-shallow source-drain junctions was used to achieve the target drain programming voltage (V sp ) for an efficient cell programming while keeping the cell breakdown voltage, BV > V sp , with tolerable leakage currents. The study shows that with properly optimised technology parameters, 65 nm SG-NOR flash memory can be achieved with an adequate cell read current, a tolerable programmed cell leakage current at the read condition and efficient write and erase times.

Depth profiling of ion implanted materials with skewed doping distributions using Fourier transform infrared spectroscopy

The applicability of a general transfer-matrix method for optical analysis of multilayers reported earlier [Katsidis and Siapkas, Appl. Opt. 41, 3978 (2002)] is being extended so as to simulate asymmetric implantation doping profiles using distributions with four moments. The sensitivity of infrared reflectance spectra regarding the variation of the first four moments of a Pearson free carrier distribution is demonstrated. Experimental data of 1.5 MeV as well as 2.5 MeV As implantation into p-Si followed by annealing at 1100 degrees C are presented, suggesting the need to use two joined Pearson IV distribution segments in the simulation of annealed profiles. A twin peak observed in the 1.5 MeV case is confirmed by Rutherford backscattering analysis.

Static and Dynamic TCAD Analysis of IMOS Performance: From the Single Device to the Circuit

Impact ionization MOSFET (IMOS) is a device that enables to reach subthreshold slopes as small as 5 mV/dec. This device has an asymmetric doping profile, and only a fraction of the channel is covered by the gate. In the first part of this paper, the purpose is to investigate the impact of some geometrical parameters on the IMOS performance: the gate length, the intrinsic length, and the Si film thickness. This study simulates a p-IMOS device on silicon-on-insulator using ATLAS. It is pointed out that the increase of the ratio LG/LIN allows a drop of the bias voltage, but involves a degradation of the subthreshold slope. A thin Si film improves the overall device performance. In the second part, the performance of an IMOS-based inverter is investigated, and for the first time an IMOS ring oscillator is simulated

Improved hot-carrier and short-channel performance in vertical nMOSFETs with graded channel doping

Graded doping profile in the channel of vertical sub-100-nm nMOSFETs was investigated in this study. Conventional single-step ion implantation was used to form the asymmetric graded doping profile in the channel. No large-angle-tilt implant is needed. The device processing is compatible with conventional CMOS technology. In a graded-channel-doping device, with the higher doping near the source, drain induced barrier lowering (DIBL) and the off-state leakage current are reduced significantly. The graded doped channel also has a lower longitudinal electric field near the drain. Therefore, hot-carrier related reliability is improved substantially with this type of device structure.

Suppression of impurity and interface-roughness back-scattering in double quantum wires: theory beyond the Born approximation

The effect of higher-order corrections to the Born approximation is studied for the previously obtained giant conductance enhancement in tunnel-coupled double quantum wires in a magnetic field by including both impurity and interface-roughness scattering. The enhancement is caused by an abrupt suppression of back-scattering of electrons which occurs when the chemical potential is in the anticrossing gap of the ground tunnel-split doublet. The calculated conductance enhancement is large, and the relative higher-order correction to the enhancement is found to be significant for long-range scattering potentials. However, this relative higher-order correction will be reduced as the range of scattering potentials becomes small. The correction depends on various effects, such as the magnetic field, electron and impurity densities, impurity positions, symmetric and asymmetric doping profiles, centre barrier thickness, and degree of interface roughness.

On the design and fabrication of novel lateral bipolar transistor in a deep-submicron technology

The performance of a npn Lateral Bipolar Transistor (LBJT), based on a minimally modified submicron MOSFET without gate oxide, was studied by means of simulations and measurements on fabricated devices. Large-tilt angle, single-sided implants were successfully used to control the breakdown voltage by tailoring an asymmetric collector doping profile and providing a lightly doped region on the collector side to increase the breakdown voltage. This was accomplished by using a base/gate pedestal as the mask for the large-tilt angle, single sided implantation in a self-aligned fashion. The individual collector–base and emitter–base junctions were found to be of excellent quality but, as expected due to the lack of carrier confinement in the base of devices built on bulk silicon, the common emitter current gain was lower than one. Two options enhancing the device performance were studied using simulators: building the LBJT on Silicon-on-Insulator (SOI) or introducing SiGe into the base. The SOI device promises to provide better performance and ease of processing when compared to the SiGe base device.

An Asymmetric Channel SOI nMOSFET for Reducing Parasitic Effects and Improving Output Characteristics

A device based on an asymmetric channel doping profile with the aim of reducing the inherent parasitic bipolar effects in fully depleted silicon-on-insulator (SOI) devices and improving the output characteristics is introduced. Measurements and two-dimensional simulations are used to study the device capabilities and limitations. (C) 1999 The Electrochemical Society. S1099-0062(99)07-087-X. All rights reserved.

Strongly asymmetric doping profiles at mask edges in high-energy ion implantation

The application of high-energy ion implantation is restricted by an asymmetric doping profile at the mask edges. As a result, buried interconnect cannot easily be formed. Moreover, the holding voltage and threshold voltage of CMOS-processes with retrograde wells may be strongly affected by this asymmetry. It arises from the 7 degrees wafer tilt, which is frequently used to avoid channeling, even in the case of nearly perpendicular (82-85 degrees ) mask edges. On the mask side, which is incoming to the ion beam, a trunk to the surface has experimentally been observed. According to two-dimensional Gaussian and advanced Monte Carlo simulations, the doping concentration in this trunk is about 20% of the maximum concentration in the case of a 85 degrees mask angle. The simulations predict the experimental results fairly well. The asymmetry effect of high energy ion implantations can also be visualized in photoresist by means of a damaged region.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>