An Asymmetrically Doped Vertical Si Biristor With Sub-1-V Operation

Abstract

Vertical biristors are small footprint ( 4F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) floating base bipolar junction transistors (BJTs) proposed for high-speed volatile memory applications. One key challenge is (i) the high latch-up voltage with Si-based biristors because of the high threshold of impact ionization (II) in Si. In this article, an epitaxial n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> /i/δp <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> /i/n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -based vertical biristor is proposed with an asymmetric doping profile that enables sub-bandgap II only in the negative polarity. First, in the negative polarity, a latch-up voltage as low as 0.5 V due to sub-bandgap II is demonstrated. Faster programming with higher bias is observed. Second, erase is demonstrated in the positive bias, where II is insignificant. Overall, a large read window ( Δ I=0.01 mA) with a low variability ( σ/μ in ΔI) for cycle-to-cycle (C2C <; 1%) and device-to-device (D2D <; 5%). Retention in excess of 1 μs is observed, taking into account C2C and D2D variations. A high endurance (> 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> cycles) is also observed. Therefore, asymmetrically doped vertical biristor is promising for very low voltage high speed memory application compared to dynamic random access memory (DRAM).