High-Speed Electronic Memories and Memory Subsystems

Prateek Asthana,Loveneet Mishra

doi:10.5772/intechopen.76257

Abstract

Memories have played a vital role in embedded system architectures over the years. A need for high-speed memory to be embedded with state-of-the-art embedded system to improve its performance is essential. This chapter focuses on the development of high-speed memories. The traditional static random access memory (SRAM) is first analyzed with its different variant in terms of static noise margin (SNM); these cells occupy a larger area as compared to dynamic random access memory (DRAM) cell, and hence, a comprehensive analysis of DRAM cell is then carried out in terms of power consumption, read and write access time, and retention time. A faster new design of P-3T1D DRAM cell is proposed which has about 50% faster reading time as compared to the traditional three-transistor DRAM cell. A complete layout of the structure is drawn along with its implementation in a practical 16-bit memory subsystem.

Highlights

In today’s modern evolving electronics, manufacturing semiconductor memory technology is an essential element
These improvements will help in gaining a dynamic random access memory (DRAM) cell design that will be capable of giving a high performance in terms of delay and power consumptions [11, 12]
The first three DRAM architectures use parasitic capacitance to store data values while the last one utilizes gated diodes to store the values. These gated diodes are generally formed from N-type metal oxide semiconductor field-effect transistor (MOSFET), but in order to reduce the power dissipation, P-type MOSFET can be utilized in their place. The advantage of this modification has been shown in comparing the various DRAM structures based on power consumption, write access time, read access time, and retention time (Figure 7)

Summary

Introduction

In today’s modern evolving electronics, manufacturing semiconductor memory technology is an essential element. 128 Advanced Electronic Circuits - Principles, Architectures and Applications on Emerging Technologies increased the necessity for semiconductor memory. In high-performance integrated circuits, static random access memories (SRAMs) have been used as on-chip memories, due to its intense access speed and compatibility with process and supply voltage. Due to aggressive complementary metal oxide semiconductor (CMOS) technology scaling, the demand for a high-performance technology has increased the amount of on-chip memory integrated into modern semiconductor devices. The continued scaling of CMOS technology has resulted in problems which were less severe in earlier generations These include process-induced variations, soft errors, transistor degradation mechanism, and so on. Static noise margin (SNM) degradation, which characterizes the data integrity of SRAM during a read operation, has driven the development of SRAM cell design into a new direction as the supply voltage reaches near the threshold voltage. We present our simulations and discuss the results [5]

SRAM 6T cell

Measurement results

Different DRAM cells

Performance comparison

Analysis of DRAM designs

Full 16-bit memory subsystem using P-3T1D DRAM cell

Findings

Conclusions