Association Process Research Articles

FPGA Implementation of Associative Processors

In order to deal with increasingly complex computing problems, an In-memory-based computation system was proposed to replace the traditional Von-Neumann architectures. In-memory computing can save the time and energy of data movement between the memory and processor to avoid the memory-wall bottleneck of traditional Von-Neumann architecture. The associative processor (AP) is such an architecture that is proposed to implement in-memory computing. Content addressable memory (CAM), as a critical part of in-memory computing, plays an important role in an AP. In this paper, we proposed a novel FPGA implementation of the AP, including the CAM and its peripheral circuits, such as the controller, data cache, instruction cache, and program counter. The design details of the whole AP architecture are described by Verilog HDL. To the best of our knowledge, this is the first work that implements an associative processor on a real-world FPGA platform.

AM4: MRAM Crossbar Based CAM/TCAM/ACAM/AP for In-Memory Computing

In-memory computing seeks to minimize data movement and alleviate the memory wall by computing in-situ, in the same place that the data is located. One of the key emerging technologies that promises to enable such computing-in-memory is spin-transfer torque magnetic tunnel junction (STT-MTJ). This paper proposes AM4, a combined STT-MTJ-based Content Addressable Memory (CAM), Ternary CAM (TCAM), approximate matching (similarity search) CAM (ACAM), and in-memory Associative Processor (AP) design, inspired by the recently announced Samsung MRAM crossbar. We demonstrate and evaluate the performance and energy-efficiency of the AM4-based AP using a variety of data intensive workloads. We show that an AM4-based AP outperforms state-of-the-art solutions both in performance (with the average speedup of about 10 ×) and energy-efficiency (by about 60 × on average).

Will computing in memory become a new dawn of associative processors?

Computer architecture faces an enormous challenge in recent years: while the demand for performance is constantly growing, the performance improvement of general-purpose CPU has almost stalled. Among the reasons are memory and power walls, due to which data transfer increasingly dominates computing. By significantly reducing data transfer, data-centric (or in-memory) computing promises to alleviate the memory and power walls. Associative processor is a non von Neumann computer invented in the 1960s but effectively cast aside until recently. It computes using associative memory in a perfect induction like fashion, using associative memory cells for both data storage and processing. Associative processor can be implemented using conventional CMOS as well as emerging memories. We show that associative processor can outperform state-of-the-art computing platforms by up to almost two orders of magnitude in a variety of data-intensive workloads.

ANALYSIS OF FEATURES OF ANALOG-TO-DIGITAL CONVERSION “DURATION-CODE”

The article presents the analysis results of the features of the analog-to-digital conversion of a continuous value as the duration of the input signal into the output digital code. Converters that work according to this principle are known as analog-code converters, and the conversion principle is a type of well-known pulse-width modulation (PWM). Information of a different nature can be used as input analog information, for example, the duration of an optical, electrical or sound signal. Specifically, the principle of this conversion with further processing of digital information uses a well-known logic-time basis, since the main operational parameter of the conversion is the duration of time, and the processing of digital data is performed according to the rules of picture logic with natural parallelism of processing on a two-dimensional field of information presentation. A feature of this approach to the conversion of input signals duration is the coding of output digital information in unit codes. In this case, two well-known unit codes are involved: unit normal and unit positional codes. This is because unit encoding is best suited for duration-to-code analog-to-digital conversion due to the quantization of the input signal duration by the trigger time of a line bistable elements. It is shown that the most acceptable implementation in terms of speed and energy consumption is the symbiosis of these two codes, since the unit normal code is faster when recording information, but loses to the unit positional code in terms of energy consumption when storing data. Taking into account the controllability of a unit positional code, the area of its effective application is the coding of the states of control devices and the addressing of the contents of storage devices, for example, as part of associative processors.

AIDA: Associative In-Memory Deep Learning Accelerator

This work presents an associative in-memory deep learning processor (AIDA) for edge devices. An associative processor is a massively parallel non-von Neumann accelerator that uses memory cells for computing; the bulk of data is never transferred outside the memory arrays for external processing. AIDA utilizes a dynamic content addressable memory for both data storage and processing, and benefits from sparsity and limited arithmetic precision, typical in modern deep neural networks. The novel in-data processing implementation designed for the AIDA accelerator achieves a speedup of 270× over an advanced central processing unit at more than three orders-of-magnitude better energy efficiency.

In-Memory Associative Processors: Tutorial, Potential, and Challenges

In-memory computing is an emerging computing paradigm that overcomes the limitations of exiting Von-Neumann computing architectures such as the memory-wall bottleneck. In such paradigm, the computations are performed directly on the data stored in the memory, which highly reduces the memory-processor communications during computation. Hence, significant speedup and energy savings could be achieved especially with data-intensive applications. Associative processors (APs) were proposed in the seventies and recently were revived thanks to the high-density memories. In this tutorial brief, we overview the functionalities and recent trends of APs in addition to the implementation of each content-addressable memory with different technologies. The AP operations and runtime complexity are also summarized. We also explain and explore the possible applications that can benefit from APs. Finally, the AP limitations, challenges, and future directions are discussed.

СИНТЕЗ ПРИСТРОЮ КЕРУВАННЯ НА БАЗІ R-АВТОМАТА ДЛЯ АСОЦІАТИВНОГО ПРОЦЕСОРА

This article discusses one of the well-known options for the synthesis of control devices with rigid logic. Such control devices provide a significant response speed compared to control devices with programmable logic, but they have a laborious process at the stages of abstract and structural synthesis of a microprogram automaton (MPA) as the basic structural model of this type of control device. Synthesis of an MPA based on a shift register as an R-automaton provides a compromise solution among the implementations of an MPA based on a parallel register as a T-automaton or a counter as a CT-automaton. This is due to the load on the memory of the MPA by reducing the complexity of the logical part of the MPA, namely its combinational scheme. The use of a specific single positional coding of the MPA states makes it possible to significantly simplify the complex process of the formation of Boolean functions corresponding to the excitation functions in the abstract synthesis of the MPA. And this, in turn, leads to a simplification of the combinational part of the MPA. At the same time, the complication of the memory part of the MPA based on the shift register leads to an increase in its bit rate without reducing the regularity of its structure. The article proposes a non-standard approach to the synthesis of a control device and develops its functional scheme. As a result, synthesis on the basis of the R - automaton of the control device structure for the associative processor confirmed the perspective of this version of MPA synthesis by simplifying the process of the corresponding abstract and structural synthesis. This is due to the simplicity of forming direct and simplified structural tables using single positional coding of MPA states. It is planned to place the developed structure of the control device in a programmable logic IC (FPGA), which will allow the placement of the entire associative processor in the FPGA. This approach will ensure the compactness of the organization and the speed of the associative processor.

GIRAF: General Purpose In-Storage Resistive Associative Framework

GIRAF is a General purpose In-storage Resistive Associative Framework based on resistive content addressable memory (RCAM), which functions simultaneously as a storage and a massively parallel associative processor. GIRAF alleviates the bandwidth wall by connecting every memory bit to processing transistors and keeping computing inside the storage arrays, thus implementing deep in-data, rather than near-data, processing. We show that GIRAF outperformed a reference computer architecture with a bandwidth-limited external storage access on a variety of data-intensive workloads. The performance of GIRAF Dot Product and Sparse Matrix-Vector multiplication exceeds the attainable performance of a reference architecture by 1200 × and 130 ×, respectively.

Design Exploration of Sensing Techniques in 2T-2R Resistive Ternary CAMs

In-Memory Computing (IMC) is considered a great candidate to replace von-Neumann computing architecture to overcome the memory wall. Ternary content-addressable memories are the main building blocks in IMC-based architectures, such as the associative processors. In this brief, we present a juxtaposition between the capacitive and resistive sensing in 2T-2R TCAMs. A Figure of Merit, function of the dynamic range, latency, and energy, is defined to have a fair comparison between the two sensing techniques. A mathematical model for the transient behavior of both sensing schemes has been derived and verified through SPICE simulations. We studied the performance with an in-memory addition application. Results from various scenarios show that the resistive sensing outperforms the capacitive one in both theoretical and application-based contexts.

Efficient Acceleration of Stencil Applications through In-Memory Computing.

The traditional computer architectures severely suffer from the bottleneck between the processing elements and memory that is the biggest barrier in front of their scalability. Nevertheless, the amount of data that applications need to process is increasing rapidly, especially after the era of big data and artificial intelligence. This fact forces new constraints in computer architecture design towards more data-centric principles. Therefore, new paradigms such as in-memory and near-memory processors have begun to emerge to counteract the memory bottleneck by bringing memory closer to computation or integrating them. Associative processors are a promising candidate for in-memory computation, which combines the processor and memory in the same location to alleviate the memory bottleneck. One of the applications that need iterative processing of a huge amount of data is stencil codes. Considering this feature, associative processors can provide a paramount advantage for stencil codes. For demonstration, two in-memory associative processor architectures for 2D stencil codes are proposed, implemented by both emerging memristor and traditional SRAM technologies. The proposed architecture achieves a promising efficiency for a variety of stencil applications and thus proves its applicability for scientific stencil computing.

IR-QNN Framework: An IR Drop-Aware Offline Training of Quantized Crossbar Arrays

Resistive Crossbar Arrays present an elegant implementation solution for Deep Neural Networks acceleration. The Matrix-Vector Multiplication, which is the corner-stone of DNNs, is carried out in $O(1)$ compared to $O(N^{2})$ steps for digital realizations of $O(log_{2}(N))$ steps for in-memory associative processors. However, the IR drop problem, caused by the inevitable interconnect wire resistance in RCAs remains a daunting challenge. In this article, we propose a fast and efficient training and validation framework to incorporate the wire resistance in Quantized DNNs, without the need for computationally extensive SPICE simulations during the training process. A fabricated four-bit Au/Al2O3/HfO2/TiN device is modelled and used within the framework with two-mapping schemes to realize the quantized weights. Efficient system-level IR-drop estimation methods are used to accelerate training. SPICE validation results show the effectiveness of the proposed method to capture the IR drop problem achieving the baseline accuracy with a 2% and 4% drop in the worst-case scenario for MNIST dataset on multilayer perceptron network and CIFAR 10 dataset on modified VGG and AlexNet networks, respectively. Other nonidealities, such as stuck-at fault defects, variability, and aging, are studied. Finally, the design considerations of the neuronal and the driver circuits are discussed.

Модель паралельного сортувальника для асоціативного процесора

The process of sorting and selecting by key is a basic procedure in many search systems such as databases and Internet search systems. At the same time, modern computing tools require efficient methods and tools which are connected with associative information processing in the development of software and hardware. Therefore, there is a need for high-speed non-computational (associative) processing of large amounts of information, which requires appropriate organization and improvement of technical means of sorting. The well-known algorithms and means for number sorting make it possible to regulate the intensity of this process and increase its efficiency using parallel devices, but they require significant hardware costs. Therefore, the purpose of further research is to develop new and improve known methods of sorting with an orientation on reducing hardware costs and increasing the speed of this process. In this paper, there has been proposed a block diagram of a sorter as a computational part of an associative processor, which has a regular logical structure and parallel-serial connections between data processing units. This greatly simplifies the placement of the sorter in a programmable logic IS (FPGA) chip. In addition, the sorter functionally implements the multifunctionality of processing numerical data arrays due to the formation of the ranks of the input array of elements. This allows determining not only the extreme elements of the numeric array but also the element occupying the average value in the sorted array, which is a necessary condition for high-speed median filtering of images. In the proposed sorter, the sorting process uses fast increment/decrement operations on the counter arrays instead of the time-consuming operation of pairwise comparison in parallel for all arrays of elements with their subsequent re-commutation.

АСОЦІАТИВНІ ПРОЦЕСОРИ З ПАРАЛЕЛЬНО-ПОСЛІДОВНОЮ ОБРОБКОЮДАНИХ

Development of associative memory and parallel methods of associative processing of numerical arrays allows to overcome the limitations of address (serial) access to memory and increase the speed of non-calculating operations. Among the methods of associative processing the most commonly used methods is processing method by bit cuts (slices), that is the simultaneous processing of the same names of bits of all words. In this paper the known variants of constructing associative processors, the base block of which is associative memory, is analyzed. An associative processor with a parallel-serial method of elements processing of a numerical array is selected. Two structures of associative processors with the ability to perform searches by key and search for a minimum / maximum in a numerical array are proposed. In the first proposed variant of the associative processor for the search by key in the numerical array, parallel-serial processing allows fixing the ratio of n operands with the key in the form of binary attributes (=, ≠) in the memory of the results on the triggers. In the second proposed version of the associative processor for search extreme numbers, the expansion of functionality is achieved by working in two modes: the search for a minimum or maximum number in an array of numbers. The feature of such processors is the using of fast register memory on counters and parallel processing without the operation of comparing elements of a numerical array. In this case, it`s possibly to combine the functionality of the two types of proposed associative processors in one associative processor due to the similarity of their structural organization and the principle of the elements processing of a numerical array using the operation of a decrement in the register memory on the counters. The basic parameters of the proposed associative processors are calculated. A comparative analysis of known and proposed associative processors is performed on indicators such as hardware complexity and time costs. A significant advantage of the proposed associative processor is the regularity of the structure and the smaller amount of hardware costs. The gain in hardware costs is important for the implementing of associative processor on promising element base - FPGA.

Power Performance Tradeoffs Using Adaptive Bit Width Adjustments on Resistive Associative Processors

Associative processors, while ideal for vector-based applications, have been limited in their use mainly due to area and energy considerations. This reality is changing due to the advent of ultra-dense resistive memories (RRAMs), allowing for area efficient implementations of in-memory associative processors. However, with the high levels of integration, issues related to power density become the major bottleneck. In this paper, we investigate approximate computing in RRAM-based associative processors as a means of enhancing energy efficiency for in-memory associative processors. A case study of a wireless communication system is considered, where fast Fourier transform (FFT) modules are widely used. The proposed manager adjusts the bit width based on the channel SNR, aiming at achieving the desired performance at a reduced energy consumption. An analytical model of system performance under the reduced bit width induced noise is presented. Based on this model, an adaptive bit width adjustment algorithm is presented that utilizes the received SNR estimates to find the optimal bit width that achieves the desired performance goals. Simulation results show that the proposed algorithm can achieve up to 45% energy savings as compared to wireless communication systems using conventional RRAM FFT associative processor.

PRINS: Processing-in-Storage Acceleration of Machine Learning

Machine learning algorithms have become a major tool in various applications. The high-performance requirements on large-scale datasets pose a challenge for traditional von Neumann architectures. We present two machine learning implementations and evaluations on PRINS, a novel processing-in-storage system based on resistive content addressable memory (ReCAM). PRINS functions simultaneously as a storage and a massively parallel associative processor. PRINS processing-in-storage resolves the bandwidth wall faced by near-data von Neumann architectures, such as three-dimensional DRAM and CPU stack or SSD with embedded CPU, by keeping the computing inside the storage arrays, thus implementing in-data, rather than near-data, processing. We show that PRINS-based processing-in-storage architecture may outperform existing in-storage designs and accelerator-based designs. Multiple performance comparisons for the ReCAM processing-in-storage implementations of $K$ -means and K -nearest neighbors are performed. Compared platforms include CPU, GPU, FPGA, and Automata Processor. We show that PRINS may achieve an order-of-magnitude speedup and improved power efficiency relative to all compared platforms.

A Two-Dimensional Associative Processor

Computing based on traditional approaches has hit its limits in terms of scalability and power consumption. For this reason, new computing paradigms have started to emerge that aim to perform operations directly in-memory to eliminate data movement costs. Even though traditional in-memory processor architectures together with emerging semiconductor technologies show promise for improving the efficiency of parallel computing, they lack some vital requirements such as flexibility and sequential execution. In this paper, a novel 2-D in-memory computing architecture is proposed. The proposed associative processing architecture is implemented by both CMOS/static random-access memory and ReRAM technologies and employed as an accelerator. As proven by circuit simulations and comparisons on a variety of benchmarks from different domains, the proposed architecture facilitates very efficient in-memory parallel computing together with a high degree of flexibility that results in faster running time in fundamental benchmarks.

Power optimization techniques for associative processors

Abstract The toughness and complexity of the computational problems which human beings tackle rise faster than the computational platforms themselves. Moreover, the dark silicon era negatively effects the traditional computational platforms and contributes unfavorably to this gap. These situations require the alternative computing paradigms, ranging from multi-core CPUs to GPUs and even untraditional paradigms such as in-memory computing. Associative processing (AP) is a promising candidate for in-memory computing where the computation is performed on the memory rows without moving the data. Even though APs propose a good solution for the memory bottleneck, their power density poses an issue because of the huge switching activity on the rows happens during the operations. In this study, we seek a low-power AP implementation by proposing architectural and instructional improvements to decrease the switching activity. The simulations on various benchmarks from different domains show that the proposed low-power AP methods provide energy reduction up to 48% with a negligible impact on the area and performance.

Approximate Memristive In-memory Computing

The bottleneck between the processing elements and memory is the biggest issue contributing to the scalability problem in computing. In-memory computation is an alternative approach that combines memory and processor in the same location, and eliminates the potential memory bottlenecks. Associative processors are a promising candidate for in-memory computation, however the existing implementations have been deemed too costly and power hungry. Approximate computing is another promising approach for energy-efficient digital system designs where it sacrifices the accuracy for the sake of energy reduction and speedup in error-resilient applications. In this study, approximate in-memory computing is introduced in memristive associative processors. Two approximate computing methodologies are proposed; bit trimming and memristance scaling. Results show that the proposed methods not only reduce energy consumption of in-memory parallel computing but also improve their performance. As compared to other existing approximate computing methodologies on different architectures (e.g., CPU, GPU, and ASIC), approximate memristive in-memory computing exhibits better results in terms of energy reduction (up to 80x) and speedup (up to 20x) on a variety of benchmarks from different domains when quality degradation is limited to 10% and it confirms that memristive associative processors provide a highly-promising platform for approximate computing.

From Processing-in-Memory to Processing-in-Storage

Near-data in-memory processing research has been gaining momentum in recent years. Typical processing-in-memory architecture places a single or several processing elements next to a volatile memory, enabling processing without transferring data to the host CPU. The increased bandwidth to and from volatile memory leads to performance gain. However processing-in-memory does not alleviate von Neumann bottleneck for big data problems, where datasets are too large to fit in main memory. We present a novel processing-in-storage system based on Resistive Content Addressable Memory ReCAM. It functions simultaneously as a mass storage and as a massively parallel associative processor. ReCAM processing-in-storage resolves the bandwidth wall by keeping computation inside the storage arrays, without transferring it up the memory hierarchy. We show that ReCAM based processing-in-storage architecture may outperform existing processing-in-memory and accelerator based designs. ReCAM processing-in-storage implementation of Smith-Waterman DNA sequence alignment reaches a speedup of almost five over a GPU cluster. An implementation of in-storage inline data deduplication is presented and shown to achieve orders of magnitude higher throughput than traditional CPU and DRAM based systems.

A 600-µW ultra-low-power associative processor for image pattern recognition employing magnetic tunnel junction-based nonvolatile memories with autonomic intelligent power-gating scheme

A novel associative processor using magnetic tunnel junction (MTJ)-based nonvolatile memories has been proposed and fabricated under a 90 nm CMOS/70 nm perpendicular-MTJ (p-MTJ) hybrid process for achieving the exceptionally low-power performance of image pattern recognition. A four-transistor 2-MTJ (4T-2MTJ) spin transfer torque magnetoresistive random access memory was adopted to completely eliminate the standby power. A self-directed intelligent power-gating (IPG) scheme specialized for this associative processor is employed to optimize the operation power by only autonomously activating currently accessed memory cells. The operations of a prototype chip at 20 MHz are demonstrated by measurement. The proposed processor can successfully carry out single texture pattern matching within 6.5 µs using 128-dimension bag-of-feature patterns, and the measured average operation power of the entire processor core is only 600 µW. Compared with the twin chip designed with 6T static random access memory, 91.2% power reductions are achieved. More than 88.0% power reductions are obtained compared with the latest associative memories. The further power performance analysis is discussed in detail, which verifies the special superiority of the proposed processor in power consumption for large-capacity memory-based VLSI systems.