Power Performance Tradeoffs Using Adaptive Bit Width Adjustments on Resistive Associative Processors

Abstract

Associative processors, while ideal for vector-based applications, have been limited in their use mainly due to area and energy considerations. This reality is changing due to the advent of ultra-dense resistive memories (RRAMs), allowing for area efficient implementations of in-memory associative processors. However, with the high levels of integration, issues related to power density become the major bottleneck. In this paper, we investigate approximate computing in RRAM-based associative processors as a means of enhancing energy efficiency for in-memory associative processors. A case study of a wireless communication system is considered, where fast Fourier transform (FFT) modules are widely used. The proposed manager adjusts the bit width based on the channel SNR, aiming at achieving the desired performance at a reduced energy consumption. An analytical model of system performance under the reduced bit width induced noise is presented. Based on this model, an adaptive bit width adjustment algorithm is presented that utilizes the received SNR estimates to find the optimal bit width that achieves the desired performance goals. Simulation results show that the proposed algorithm can achieve up to 45% energy savings as compared to wireless communication systems using conventional RRAM FFT associative processor.