Assembly Process Development Research Articles

ITER TF Load Transfer and Precompression Assembly Process Development

ITER TF Load Transfer and Precompression Assembly Process Development

Investigating the impact of different solder alloy materials during laser soldering process

PurposeThis study aims to investigate the influence of different solder alloy materials on passive devices during laser soldering process. Solder alloy material has been found to significantly influence the solder joint’s quality, such as void formation that can lead to cracks, filling time that affects productivity and fillet shape that determines the solder joint’s reliability.Design/methodology/approachFinite volume method (FVM)-based simulation that was validated using real laser soldering experiment is used to evaluate the effect of various solder alloy materials, including SAC305, SAC387, SAC396 and SAC405 in laser soldering. These solders are commonly used to assemble the pin-through hole (PTH) capacitor onto the printed circuit board.FindingsThe simulation results show how the void ratio, filling time and flow characteristics of different solder alloy materials affect the quality of the solder joint. The optimal solder alloy is SAC396 due to its low void ratio of 1.95%, fastest filling time (1.3 s) to fill a 98% PTH barrel and excellent flow characteristics. The results give the ideal setting for the parameters that can increase the effectiveness of the laser soldering process, which include reducing filling time from 2.2 s to less than 1.5 s while maintaining a high-quality solder joint with a void ratio of less than 2%. Industries that emphasize reliable soldering and effective joint formation gain the advantage of minimal occurrence of void formation, quick filling time and exceptional flowability offered by this solution.Practical implicationsThis research is expected not only to improve solder joint reliability but also to drive advancements in laser soldering technology, supporting the development of efficient and reliable microelectronics assembly processes for future electronic devices. The optimized laser soldering material will enable the production of superior passive devices, meeting the growing demands of the electronics market for smaller, high-performance electronic products.Originality/valueThe comparison of different solder alloy materials for PTH capacitor assembly during the laser soldering process has not been reported to date. Additionally, volume of fluid numerical analysis of the quality and reliability of different solder alloy joints has never been conducted on real PTH capacitor assemblies.

Consideration of handedness in human-robot collaboration

In the design of assembly workplaces, considerations regarding handedness and ergonomics play a crucial role. The emergence of human-robot collaboration presents an innovative avenue for enhancing the ergonomic aspects of manual assembly tasks. While initial applications have demonstrated improvements in lifting and holding activities, they often overlook the influence of human handedness. This paper advocates for the adoption of adaptive assembly processes, which offer simple and intuitive robot programming options to enhance workflow efficiency and reduce stress. This study is grounded in two investigations conducted at the Bremen Institute for Mechanical Engineering. The first study, a pilot investigation, aimed to identify indicators of the influence of handedness and ergonomics, laying the groundwork for further research. Building upon these findings, the second study delves into the interaction between workers and collaborative robots during assembly operations. Data collected from 50 participants form the basis for statistical analysis, providing insights into performance factors and self-assessment, as well as external evaluations of ergonomics. A notable finding of this study challenges the assumption of mirrored behavior between presumed left-handed and right-handed individuals. Additionally, the study identifies a subgroup of participants with ambiguous handedness, suggesting a lack of training in their natural handedness. Through these investigations, this paper contributes to our understanding of the intricate relationship between handedness, ergonomics, and human-robot collaboration in assembly workplaces. By addressing these factors comprehensively, we can pave the way for the development of more inclusive and efficient assembly processes.

Integrated Micro‐Scale Concentrating Photovoltaics: A Scalable Path Toward High‐Efficiency, Low‐Cost Solar Power

The global energy market is seeing increases in the electricity demand of a couple of percentage points annually. The photovoltaic (PV) industry is also growing rapidly every year. One of the PV technologies is concentrator photovoltaics (CPV). CPV uses high‐efficiency multijunction solar cells and optics to concentrate sunlight, thereby significantly reducing the amount of semiconductor material needed. Yet, due to the high upfont manufacturing cost of CPV, it currently does not offer a competitive price against silicon PV. With this a new branch is introduced to the industry, micro‐CPV, which can be broadly explained as the miniaturization of the solar cells and optical components. The motivation for micro‐CPV is lowering the cost by decreasing the material volume and enabling new system architectures and high‐throughput manufacturing methods, while still maintaining high electrical efficiencies, taking advantage of a lower thermal load, shorter optical paths, lower resistive losses, and lower material volumes. Herein, a comprehensive review of the technological advances is presented, key synergies between micro‐CPV and other industries sharing similar challenges are identified, exemplified by micro‐light emitting diodes display manufacturing. New assembly process development in these industries will facilitate commercial adoption of micro‐CPV with continued miniaturization while driving down the cost.

Fine-pitch Copper Pillar Flip Chips in High Reliability Applications

Abstract To keep up with the demands for smaller antennas with increased performance and decreased costs, most next generation architectures mandate higher IC (integrated circuit) chip integration. Compared to conventional packaging configurations, advanced chip packaging technologies, such as 2.5D and 3D, offer greater chip compatibility and lower power consumption. Given these advantages, the adoption of advanced packaging is inevitable. Within advanced packaging, the copper pillar interconnect is a key enabling technology, and the next logical step. This technology offers several benefits, including improved electromigration resistance, improved electrical and thermal conductivity, simplified underbump metallization (UBM), and higher I/O (input/output) density. The fine pitches that copper pillars allow helps the technology to supersede solder bump technology, which reaches its lowest pitch around 40 microns. Finer pitches allow for a higher I/O count, which increases performance. In this work, assembly of ultra-thin MMIC (monolithic microwave integrated circuit) GaN (Gallium Nitride) fine-pitch copper pillar flip chip assemblies on high density interposers was successfully demonstrated. Using 150μm pitch copper pillar flip chip, the assembly processes for both organic PCB (printed circuit board) and silicon interposers were evaluated, with both an ENIG (Electroless Nickel Immersion Gold) and eutectic tin-lead solder pad finish evaluated. For the 2D/2.5D/3D assembly process development, a standard in-house pick and place tool was used, followed by mass solder reflow, finished with an underfill for reliability test. The interconnect robustness was determined by die pull strengths, a flux stamping investigation, and cross-sections. Complete reliability and qualification test data on GaN copper pillar flip chip 2D assembly was completed, including 700 temperature cycles and UHAST (unbiased highly accelerated temperature/humidity stress test).

Application of the Deep CNN-Based Method in Industrial System for Wire Marking Identification

Industry 4.0, a term invented by Wolfgang Wahlster in Germany, is celebrating its 10th anniversary in 2021. Still, the digitalization of the production environment is one of the hottest topics in the computer science departments at universities and companies. Optimization of production processes or redefinition of the production concepts is meaningful in light of the current industrial and research agendas. Both the mentioned optimization and redefinition are considered in numerous subtopics and technologies. One of the most significant topics in these areas is the newest findings and applications of artificial intelligence (AI)—machine learning (ML) and deep convolutional neural networks (DCNNs). The authors invented a method and device that supports the wiring assembly in the control cabinet production process, namely, the Wire Label Reader (WLR) industrial system. The implementation of this device was a big technical challenge. It required very advanced IT technologies, ML, image recognition, and DCNN as well. This paper focuses on an in-depth description of the underlying methodology of this device, its construction, and foremostly, the assembly industrial processes, through which this device is implemented. It was significant for the authors to validate the usability of the device within mentioned production processes and to express both advantages and challenges connected to such assembly process development. The authors noted that in-depth studies connected to the effects of AI applications in the presented area are sparse. Further, the idea of the WLR device is presented while also including results of DCNN training (with recognition results of 99.7% although challenging conditions), the device implementation in the wire assembly production process, and its users’ opinions. The authors have analyzed how the WLR affects assembly process time and energy consumption, and accordingly, the advantages and challenges of the device. Among the most impressive results of the WLR implementation in the assembly process one can be mentioned—the device ensures significant process time reduction regardless of the number of characters printed on a wire.

Optimized process chain for flexible and automated aircraft interior production

The growing aviation market puts first tier suppliers of cabin interior under great pressure. Historically grown, poorly optimized manual processes limit the production rate of highly individualized interior components, required by the airlines. Different automated approaches offer solutions for high rate production of standardized lightweight structures. However, those solutions can not be adapted to individual sandwich panels. In this paper, first, the manual process chain is analyzed. Necessary components and features are identified and processes are evaluated with respect to automatability, accuracy, as well as flexibility and design freedom. Based on the analysis, a concept for the automated manufacturing of highly individual, flat sandwich panels with a standardized, digital process is developed. A discussion of the results shows that the presented process meets the targeted objectives, allows a simplified panel design and offers great potential for the development of digital assembly processes with low risk to fail aviation certification.

Worker assistance systems and assembly process maturity in the prototype and pre-series production

In order to minimize time-to-market, the development and planning of automotive assembly processes needs to be conducted in early product development stages under high uncertainty, with frequent changes and increasing time and cost pressure. Nonetheless, the resulting processes at the time of handover to the series production need to be mature, thoroughly tested and optimized to minimize problems and delays in the ramp-up. Recently, assistance systems for the manual assembly have received extensive attention in research and practice. However, they were almost exclusively applied to the series production, while little regard was dedicated to the potential such systems can offer for development and planning. Therefore, this paper presents an approach to leverage worker assistance systems for the assembly process development and evaluation during the prototype assembly in series development. A general approach and design for such a system is described and observations from a company are presented where a corresponding solution was piloted.

Case study: Application of Design for Automated Assembly methods in the development of an electronic product from early design to design freeze

The paper discusses experiences from a concurrent product- and automated assembly process-development in a manufacturing company from early design to design freeze. The product is a compact product consisting of a plastic casing housing electronic components which is currently entering production. The company is a high-tech manufacturer operating in a high-cost country delivering safety products in a business to business market. The case study is based on project documentation, analyses of product and assembly concept, lab tests as well as dialogue with the manufacturer and the product designer. The main author was involved in the automated assembly process development and Design for Automatic Assembly (DFAA). The product and the automated assembly line were designed in parallel, throughout the entire product development process; from idea and concept development until the pre-production stages. In the early stages of the project the product was redesigned on a frequent basis, and each new design was evaluated for its automated manufacturability. In this process several DFAA methods were applied. The product designers also produced several prototypes by a plastic additive technology (3D printers) that were assembled in a prototype automated cell to assess product design and assembly solutions, and to reveal weaknesses that were not detected in the analysis. This paper compares the different DFAA methods used such as DFA2, as well as a custom DFAA review spreadsheet. Additionally, the paper discusses the interaction between product design and production process design, and effects on the outcome. Finally, the paper suggests design process improvements and guidelines.

Micromachining on and of Transparent Polymers for Patterning Electrodes and Growing Electrically Active Cells for Biosensor Applications.

We report on microfabrication and assembly process development on transparent, biocompatible polymers for patterning electrodes and growing electrically active cells for in vitro cell-based biosensor applications. Such biosensors are typically fabricated on silicon or glass wafers with traditional microelectronic processes that can be cost-prohibitive without imparting necessary biological traits on the devices, such as transparency and compatibility for the measurement of electrical activity of electrogenic cells and other biological functions. We have developed and optimized several methods that utilize traditional micromachining and non-traditional approaches such as printed circuit board (PCB) processing for fabrication of electrodes and growing cells on the transparent polymers polyethylene naphthalate (PEN) and polyethylene terephthalate (PET). PEN-based biosensors are fabricated utilizing lithography, metal lift-off, electroplating, wire bonding, inkjet printing, conformal polymer deposition and laser micromachining, while PET-based biosensors are fabricated utilizing post-processing technologies on modified PCBs. The PEN-based biosensors demonstrate 85–100% yield of microelectrodes, and 1-kHz impedance of 59.6 kOhms in a manner comparable to other traditional approaches, with excellent biofunctionality established with an ATP assay. Additional process characterization of the microelectrodes depicts expected metal integrity and trace widths and thicknesses. PET-based biosensors are optimized for a membrane bow of 6.9 to 15.75 µm and 92% electrode yield on a large area. Additional qualitative optical assay for biomaterial recognition with transmitted light microscopy and growth of rat cortical cells for 7 days in vitro (DIV) targeted at biological functionalities such as electrophysiology measurements are demonstrated in this paper.

Addressing Flux Dip Challenges for 3-D Integrated Large Die, Ultrafine Pitch Interconnect

The requirement for closely coupled, highly integrated circuits in the semiconductor industry has spawned alternative packaging innovations such as 2.5-D/3-D integration. The incredible potential of this alternative comes with great challenges, not the least of which is the unprecedented reduction in package interconnection pitch. Market acceptance of new fine-pitch microelectronic products is strongly dependent on the development of flawless assembly processes that align with the traditional Moore-like expectation of higher performance without cost penalty. One such process is the application of flux to the interconnect surfaces to achieve effective joining. Insufficient flux quantity or flux activity can impede the formation of solid, reliable joints, whereas excessive quantities or activity can cause solder bridging or difficulties with downstream operations such as residue cleaning or underfill reinforcement. This delicate balance, already complex for traditional chip joining, is further challenged by the geometrical and spatial reductions imposed by pitch miniaturization, especially where large die, with over 100,000 interconnects, are concerned. This article presents an overall development protocol to evolving a flux dipping operation to production-level thermocompression assembly of large die (8 × 11 × 0.780 mm) with 11,343 ultrafine pitch (62 μm) copper pillar interconnections. After reviewing the state of the art for fluxing technology and detailing the specific technical issues, we present and defend the chosen flux application approach with its corresponding parameters of interest. Physical and chemical characterization results for selected flux material candidates are reported in conjunction with an analysis of how their properties correlate to the flux dip application parameters. As part of this fundamental understanding, we investigate and report on flux dip coating behavior and how it compares to other industrial dip coating applications. Finally, the results of process assembly experiments in a production-type environment are reviewed and discussed with respect to the previous characterizations. These experiments span downstream assembly process compatibility (i.e., cleaning and underfill) as well as product reliability.

Addressing Flux Dip Challenges for 3D Integrated Large Die, Ultra-fine Pitch Interconnect

Abstract The requirement for closely coupled, highly integrated circuits in the semiconductor industry has spawned alternative packaging innovations such as 2.5D/3D integration. The incredible potential of this alternative comes with great challenges, not the least of which is the unprecedented reduction in package interconnection pitch. Market acceptance of new fine-pitch microelectronic products is strongly dependent upon the development of flawless assembly processes that align with the traditional Moore-like expectation of higher performance without cost penalty. One such process is the application of flux to the interconnect surfaces in order to achieve effective joining. Insufficient flux quantity or flux activity can impede the formation of solid, reliable joints, while excessive quantities or activity can cause solder bridging or difficulties with downstream operations such as residue cleaning or underfill reinforcement. This delicate balance, already complex for traditional chip joining, is further challenged by the geometrical and spatial reductions imposed by pitch miniaturization, especially where large die, with over 100,000 interconnects, are concerned. This paper presents an overall development protocol to evolving a flux dipping operation to production-level thermocompression assembly of large die with ultra-fine pitch (60 μm) copper pillar interconnections. After reviewing the state of the art for fluxing technology and detailing the specific technical issues, we present and defend the chosen flux application approach with its corresponding parameters of interest. Physical and chemical characterization results for selected flux material candidates are reported in conjunction with an analysis of how their properties correlate to the flux dip application parameters. As part of this fundamental understanding, we investigate and report on flux dip coating behaviour and how it compares to other industrial dip coating applications. Finally, the results of process assembly experiments in a production-type environment are reviewed and discussed with respect to the previous characterizations. These experiments span downstream assembly process compatibility (i.e. cleaning and underfill) as well as product reliability.

Detection and Identification of Assembly Characteristics of Lithium-Ion Battery Modules Using RGB-D Imagery

A large diversity of product variants often leads to decision making problems during product and assembly process development. This paper presents a novel method that is used to quickly gather assembly characteristics of product variants for the enrichment of criteria for decision making methods and acceleration of assembly process planning. The collection of data is accomplished through a depth camera-based surveillance of a flexible, reconfigurable assembly workspace. For the surveillance, a robust and efficient motion tracking approach is developed theoretically and implemented practically in a software environment. The evaluation of the presented method is done by assembling different lithium-ion battery variants.

Ceramic Column Grid Array Assembly Qualification and Reliability Analysis for Space Missions

Ceramic column grid array (CCGA) devices are presently the state-of-the-art packaging solutions for advanced computational electronics. For high-reliability applications incorporating thermal and vibration loads, CCGA columns provide more compliant interconnect during thermal cycle of the assembly and improve interconnection reliability by design. Assembly of such high interconnect count device requires process development and qualification prior to their deployment in space borne payloads. CCGA assembly process development, comprehensive assembly qualification tests (thermal cycling, vibration, humidity, microsectioning, and 3-D Computed Tomography X-ray inspection), and reliability estimation are presented in this paper.

Package-on-Package Design and Assembly Process Development for Size Reduction

A package-on-package configuration was designed and assembled to replicate an off-the-shelf RF device to reduce its footprint, height and thus volume. The footprint was reduced by 60% and the height was reduced by 32% resulting in 73% reduction in volume. An efficient assembly process was developed using information form electrical, thermal and mechanical simulations.

Flip chip assembly of thinned chips for hybrid pixel detector applications

There is a steady trend to ultra-thin microelectronic devices. Especially for future particle detector systems a reduced readout chip thickness is required to limit the loss of tracking precision due to scattering. The reduction of silicon thickness is performed at wafer level in a two-step thinning process. To minimize the risk of wafer breakage the thinned wafer needs to be handled by a carrier during the whole process chain of wafer bumping. Another key process is the flip chip assembly of thinned readout chips onto thin sensor tiles. Besides the prevention of silicon breakage the minimization of chip warpage is one additional task for a high yield and reliable flip chip process. A new technology using glass carrier wafer will be described in detail. The main advantage of this technology is the combination of a carrier support during wafer processing and the chip support during flip chip assembly. For that a glass wafer is glue-bonded onto the backside of the thinned readout chip wafer. After the bump deposition process the glass-readout chip stack is diced in one step. Finally the glass carrier chip is released by laser illumination after flip chip assembly of the readout chip onto sensor tile. The results of the flip chip assembly process development for the ATLAS IBL upgrade are described more in detail. The new ATLAS FEI4B chip with a size of 20 × 19 mm2 is flip chip bonded with a thickness of only 150 μm, but the capability of this technology has been demonstrated on hybrid modules with a reduced readout chip thickness of down to 50 μm which is a major step for ultra-thin electronic systems.

Design and Realization Aspects of 1-THz Cascade Backward Wave Amplifier Based on Double Corrugated Waveguide

The design and fabrication challenges in the first ever attempt to realize a 1-THz vacuum tube amplifier are described. Implementation of innovative solutions including a slow-wave structure in the form of a double corrugated waveguide, lateral tapered input and output couplers, deep X-ray LIGA fabrication process, and a cascade architecture of the backward wave amplifier are discussed. New knowledge in the field of terahertz vacuum devices brought by intensive simulations and development of advanced fabrication and assembly processes of the micro-structures is highlighted.

Multichip Embedding Technology Using Fine-Pitch Cu–Cu Interconnections

Increasing performance and functional density while maintaining low cost is a catalyst for technological progress in the field of packaging. From flip-chip with solder to a hybrid approach of copper and solder, many methods have been created to reach this objective. The 3-D Packaging Research Center at Georgia Tech has been revolutionizing interconnection technology with the multichip embedding chip-last approach, which utilizes ultrathin adhesive-bonded copper bumps to enable ultrafine-pitch chip-to-package interconnections. This technology has been proven to be highly reliable using a low-cost low-temperature direct copper-to-copper bonding approach at 30-μm pitch and ~20-μm standoff height copper-to-copper interconnections. This interconnection method provides a platform for integration with flip-chip packages through its proven ability to work well with different die sizes and thicknesses bonded to the surface of ultrathin organic substrates. The next step in advancing the chip-last approach is to investigate chip embedding at the single-chip and multichip levels. Consequently, this paper focuses on: 1) the design and fabrication of the test vehicle to examine the reliability of the previously demonstrated copper-to-copper interconnections after embedding a thin die in an organic substrate, and 2) assembly process development and reliability data for the interconnections. Specifically, advances in the assembly process include: 1) a novel method to perform chip-last assembly at the panel level leading to a 10-15 times reduction in assembly time per die, and 2) an improved two-step assembly process to achieve simultaneous die embedding and cavity planarization. This embedding technology and its advancements not only allow actives to be embedded in organic substrates but also enables higher functional integration at high-throughput, making chip-last adhesive bonding with low-profile copper-to-copper interconnections a robust chip embedding solution for the next generation of highly integrated heterogeneous subsystems.

Evaluation of image reconstruction algorithms for non-destructive characterization of thermal interfaces

Thermal interfaces are encountered in many thermal management applications and interface materials are used to minimize thermal contact resistance resulting from solid–solid contact. For opto-electronic devices the quality of the thermal interface is critical for removing the generated heat for proper thermal management. Defects in the thermal interface introduce additional thermal resistance in the thermal path, and must be prevented. Detection of defects in the thermal interfaces becomes critical during the assembly process development. Imaging techniques such as X-ray computerized tomography, or scanning acoustic microscopy that require expensive equipment and significant processing time is necessary. Thermal tomography in conjunction to IR thermometry can be used as a lower cost alternative to these techniques. The feasibility of thermal tomography for non-destructive characterization of thermal interfaces is presented by considering different image reconstruction algorithms. The algorithms considered are the iterative perturbation algorithm, Levenberg–Marquardt algorithm and the regularized Newton–Gauss algorithm, and they were found to be capable of characterizing the thermal interface layer.

Process Development and Reliability of Microbumps

The use of flip-chip bonding technology on gold-tin (AuSn) microbumps for flip-chip packaging is becoming increasingly important in the electronics industry. Some of the main advantages of AuSn system over solder flip-chip technology are suitability for very fine pitch interconnection and fluxless bonding. Fluxless flip-chip assembly is in demand especially for medical applications and optoelectonics packaging. Here, we report the assembly process development of a silicon stacked module assembled with AuSn microbumps to meet the stringent reliability. The effects of bond pressure distribution, bond temperature and alignment accuracy were found to be critical in this stacked silicon using AuSn microbumps. A three-factor design of experiment was carried out to investigate the effects of assembly parameters such as bonding pressure, temperature and time on contact resistance and AuSn solder wetting on the electroless nickel and gold under bump metallization. Results showed that higher bond force is undesirable and contributes to passivation cracking and deformed AuSn joint with AuSn solder being squeezed out of the joint during bonding. The reliability result of the flip-chip assembly of stacked silicon module using AuSn microbumps was presented.