Array Circuit Research Articles

One-dimensional equivalent circuit for ultrasonic transducer arrays

Ultrasonic transducer arrays utilized in medical imaging and NDT applications are generally composed of several piezoelectric elements arranged in 1D or 2D ways. These structures are usually modeled by sophisticated 2D and 3D numerical methods. In this paper, a one-dimensional electromechanical circuit inspired from the Mason’s simplified one, is utilized to model a transducer array composed of seven piezoelectric elements made of PZ27. The validity and the limitations of the model are pointed out by comparing the computed electrical impedances and displacements to the ones obtained experimentally. The novelty of our approach is to offer a simple electrical method to analyze the physical behavior of piezoelectric transducer arrays. This one, allows the study of the mechanical crosstalk between array elements and does not need expensive experiments such as displacement measurements using a laser vibrometer. Finally, the electrical model is expected to be utilized in harmonic and transient domain in order the reduce the crosstalk phenomenon.

Framework for High-Performance Video Acquisition and Processing in MTCA.4 Form Factor

The presented framework enables capturing video streams from cameras with a Camera Link interface. It is designed for scalable high-reliability industrial and scientific applications. The solution performs data capture, optionally processing it, and delivers it to a host CPU. It consists of an MTCA.4-compliant frame grabber, its firmware, and a set of software components supporting several different cameras. The framework is focused on Xilinx 7-Series field-programmable gate array (FPGA) circuits. These have I/O pins fast enough to deserialize the Camera Link streams without use of any external components. The reference implementation runs on a hardware platform composed of a dual-slot FMC carrier module equipped with a modern Artix-7 FPGA and up to two Camera Link pass-through modules. The video stream is written to the host computer memory by a custom scatter-gather direct memory access (DMA) engine developed at the Department of Microelectronics and Computer Science (DMCS) of Lodz University of Technology. The framework also includes complete software support consisting of a Linux device driver, application programming interface libraries as well as console and graphical user applications. The proposed video acquisition solution is the world's first Camera Link frame grabber for the MTCA.4 architecture. It enables collecting data from the camera using the top performance 80-bit Camera Link interface, offering 6.8 Gb/s of raw image data throughput. The solution was tested with a number of commercially available cameras.

An Improved Liquid Metal Mask Printing enabled Fast Fabrication of Wearable Electronics on Fabrics.

In this paper, a new improved mask printing method of liquid metal is developed, which realizes the fast fabrication of flexible electronics on fabrics. Here, polymethacrylates (PMA) glue is printed on fabrics to improve the adhesion effect of liquid metal (EGaIn) on fabrics. Combined with mask printing, liquid metal can be directly and rapidly printed on the fabrics with PMA glue to manufacture flexible electronics, such as LED array circuit, strain sensor and temperature monitoring circuit. With combined the advantages of favorable stretchability and rapid manufacture, the improved liquid metal mask printing method provides an approach with valuable prospects for individualized wearable health care devices. Besides, this method has extensive application prospect in mass production of smart electronic fabrics.

Practical fault resilient hardware implementations of AES

Security is a challenging issue in resource-constrained applications, e.g. in an embedded system. This study focused on practical lightweight fault-tolerant strategies for hardware implementation of Advanced Encryption Standard (AES) to mitigate the-reliability issue of secure architectures. In this work, a-fault-tolerant architecture called configurable fault-tolerant AES (CFTA), and its variants, called robust CFTA (R-CFTA), R-CFTA+, high throughput CFTA (HT-CFTA), HT-CFTA4R, HT-CFTA8R, and HT-CFTA+, are introduced. Proposed approaches exploit the-inherent parallel architecture of AES for employing redundancy at low cost. CFTA and HT-CFTA can tolerate all single permanent and transient faults in the-AES blocks and also all multiple permanent and transient faults in the-same block. R-CFTA upgrades the-fault-tolerant aspect of CFTA and HT-CFTA and it is also able to tolerate all single- and multiple-transient faults in two AES functional blocks during a round. The proof is provided to show the fault masking ability of provided architectures. Furthermore, R-CFTA+ and HT-CFTA+, which are suitable for high-security sensitive applications are suggested. In addition, the proposed fault-tolerant designs are implemented on both field programmable gate array and application-specific integrated circuit platforms, and their implementation area, frequency, and throughput are discussed and compared with other related works. Moreover, system-efficiency, as an important design metric, is reported for proposed structures.

Active balancing of lithium‐ion battery cells using WPT as an energy carrier

This study develops a novel equaliser by combining wireless power transmission (WPT) and switch array for series-connected batteries. The physical isolation achieved by WPT can offer unique benefits that traditional equalisers can hardly provide. Parameters of the WPT system are properly designed to achieve an equivalent constant-current output, which can maximise the speed of balance and ensure the health of batteries. This methodology can ensure each battery is connected independently to the inverter through the switch array circuit. Therefore, balancing for either a single battery or multiple batteries can be achieved. In the experiment, the prototype system is built. Experimental results show that the proposed equalisation system can achieve high overall system efficiency (above 87.2%) when balancing four series-connected battery modules.

Chiral Voltage Propagation and Calibration in a Topolectrical Chern Circuit.

We propose an electric circuit array with topologically protected unidirectional voltage modes at its boundary. Instead of external bias fields or Floquet engineering, we employ negative impedance converters with current inversion (INICs) to accomplish a nonreciprocal, time-reversal symmetry-broken electronic network we call a topolectrical Chern circuit (TCC). The TCC features an admittance bulk gap fully tunable via the resistors used in the INICs, along with a chiral voltage boundary mode reminiscent of the Berry flux monopole present in the admittance band structure. The active circuit elements in the TCC can be calibrated to compensate for dissipative loss.

Influence of Surface Roughness on Microring-Based Phase Shifters

The dramatic phase shift and high transmission enable the over-coupled microring resonators for efficient pure phase modulator. Its compact size is especially valuable for large-scale coherent all-optical logic circuit and phase arrays on chip. In this letter, we examine the impact of fabrication imperfection-induced mode splitting for the microring-based phase shifters. We initially measure the phase shift in mode-splitting ring resonators, with the results fitted by coupled mode theory (CMT). Based on the extracted parameter space from the experimental data, we then studied the influence of surface roughness-induced photon scattering for the maximum phase shift and insertion loss of the microring resonators. Surface roughness pushes the ring-waveguide coupling condition from over-coupling toward under-coupling region. The maximum phase shift reduces from $2\pi $ to only 1 rad accordingly.

Switching Event Detection and Self-Termination Programming Circuit for Energy Efficient ReRAM Memory Arrays

Energy efficiency remains a challenge for the design of non-volatile resistive memories (ReRAMs) arrays. This memory technology suffers from intrinsic variability in switching speed, programming voltages, and resistance levels. The programming conditions of memory elements (e.g., pulse widths and amplitudes) must cover the tail bits to avoid programming failures. Switching time of ReRAMs shows wide distributions. Therefore, fast cells are subjects for electrical stress after their switching and energy waste since programming currents are typically large for this technology (tens of $ {\mu }\text{A}$ ). In this brief, we present a write termination (WT) circuit to stop the programming operation when the switching event occurs in the selected memory element. The proposed design is sensitive to current variations that take place when the memory element switches between two different resistance states (low resistance state and high resistance state). This WT scheme reduces the power consumption by 97+%, 93+%, and 65+% during Forming, RESET and SET operations respectively. Our estimations show that area efficiency of 70% for a memory array is achievable when the presented WT circuit is integrated in near-memory peripheries. The demonstrated WT circuit is suitable for different ReRAM technologies with small overhead penalty and shows robustness against CMOS and ReRAM variabilities.

K/Ka-Band Very High Data-Rate Receivers: A Viable Solution for Future Moon Exploration Missions

This paper presents a feasibility study for a very high data rate receiver operating in the K/Ka-band suitable to future Moon exploration missions. The receiver specifications are outlined starting from the mission scenario and from a careful system analysis. The designed architecture uses a low noise front-end to down-convert the incoming K/Ka-band signal into a 3.7 GHz intermediate frequency (IF). For maximum flexibility, a software defined radio (SDR) is adopted for the I/Q demodulation and for the analog to digital conversion (ADC). The decoding operations and the data interface are carried out by a processor based on field programmable gate array (FPGA) circuits. To experimentally verify the above concepts, a preliminary front-end breadboard is implemented, operating between 27.5 and 30 GHz. The breadboard, which uses components off the shelf (COTS) and evaluation boards (EVBs), is characterized by a 46 dB gain, a 3.4 dB noise figure and a − 37 dBm input-referred 1 dB compression point. Finally, a 40 Msym / s quadrature phase shift keying (QPSK) signal is demodulated by means of a commercially available SDR, demonstrating the above concept. The importance of these results is that they have been obtained exploiting a class of miniaturized and low cost microwave integrated circuits currently available on the market, opening the way to a dense communication infrastructure on cislunar space.

A self-healing strategy with fault-cell reutilization of bio-inspired hardware

The self-healing strategy is a key component in designing the bio-inspired embryonics circuit with the structure of cell arrays. However, the existing self-healing strategies of embryonics circuits mainly focus on permanent faults inside the modules of cells such as the function module and the configuration register, while little attention is paid to transient faults. From the point of view of obtaining high efficiency of hardware utilization, it would be a huge waste of hardware resources by permanent elimination when a cell only suffers a transient fault which can be repaired by a configuration mechanism. A new self-healing strategy, the Fault-Cell Reutilization Self-healing Strategy (FCRSS) which presents a method for reusing transient fault cells, is proposed in this paper. The circuit structures of all the modules in the cells are described in detail. In the new strategy, two processes of elimination and reconfiguration are combined. Within the process of fault-cell elimination, cells with transient faults in the embryonics circuit array could be reused simultaneously to replace the functions of the cells on their left side in the same row. Therefore, transient fault-cells in a transparent state can be reconfigured to realize the fault-cell reutilization. Finally, a circuit simulation, resource consumption, a reliability analysis and a detailed normalization analysis are presented. The FCRSS can improve the hardware utilization rate and system reliability at the expense of a small amount of hardware resources and reconfiguration time. Following the conclusion, the method of determining the optimal self-healing strategy is presented according to the environmental conditions.

Electro-static discharge failure analysis and design optimization of gate-driver on array circuit in InGaZnO thin film transistor backplane

There is a risk of InGaZnO thin film transistor (IGZO TFT) failure, especially electro-static discharge (ESD) damage of gate driver on array (GOA) circuits, due to the combination of Cu interconnect, InGaZnO (IGZO) active layer and SiN<i><sub>x</sub></i>/SiO<sub>2</sub> insulating layer used to realize large-scale ultra-high resolution display. It is found that the IGZO TFT damage position caused by ESD occurs between the source/drain metal layer and the gate insulator. The Cu metal of gate electrode diffuses into the gate insulator of SiN<sub><i>x</i></sub>/SiO<sub>2</sub>. The closer to the ESD damage area the IGZO TFT is, the more serious the negative bias of its threshold voltage (<i>V</i><sub>th</sub>) is until the device is fully turned on. The IGZO TFT with a large channel width-to-length ratio(<i>W</i>/<i>L</i>) in GOA circuit results in a serious negative bias of threshold voltage. In this paper, the ESD failure problem of GOA circuit in the IGZO TFT backplane is systematically analyzed by combining the ESD device level analysis with the system level analysis, which combines IGZO TFT device technology, difference in metal density between GOA region and active area on backplane, non-uniform thickness distribution of gate metal layer and gate insulator and so on. In the analysis of ESD device level, we propose that the diffusion of Cu metal from gate electrode into SiN<sub><i>x</i></sub>/SiO<sub>2</sub> leads to the decrease of effective gate insulator layer, and that the built-in space charge effect leads to the decrease of the anti-ESD damage ability of IGZO TFT. In the analysis of ESD system level, we propose that the density of metal layers in GOA region is 4.5 times higher than that in active area of display panel, which makes the flatness of metal layer in GOA region worse. The non-uniformity of thickness of Cu metal film, SiN<i><sub>x</sub></i> film and SiO<sub>2</sub> film around glass substrate lead to the position dependence of the anti-ESD damage ability of IGZO TFT in the GOA region. If there is a transition zone of film thickness change in IGZO TFT with large area, the ESD failure will occur easily. Accordingly, we propose to split large area IGZO TFT into several sub-TFT structures, which can effectively improve the ESD failure.

Robust Direct Torque Control with Super‐Twisting Sliding Mode Control for an Induction Motor Drive

A field‐programmable gate array‐ (FPGA‐) based nonlinear Direct Torque Control (DTC) associated with Space Vector Modulation (SVM), Input‐Output Feedback Linearization (IOFL), and second‐order super‐twisting speed controller is proposed to control an induction motor drive. First, the nonlinear IOFL is proposed to achieve a decoupled flux and torque control and the SVM technique is used to control the inverter switching frequency which reduces the torque ripples and noise. Next, to enhance the speed regulation, a super‐twisting speed controller is added to an SVM‐DTC‐IOFL scheme. The nonlinear SVM‐DTC‐IOFL ensures a high dynamic response, good robustness under the external load disturbances. The Lyapunov theory is used to analyze the system stability. Then, this paper presents the interest of implementing the suggested SVM‐DTC‐IOFL using a Field‐Programmable Gate Array (FPGA) circuit. The main interest of the FPGA‐implementation is the reduction of the control loop delay, which is evaluated to a few microseconds, thanks to the parallel processing offered by the FPGA. The performances of the proposed control algorithm are investigated by digital simulation using the Xilinx system generator tool and an experimental implementation utilizing an FPGA‐Virtex‐5‐ML507.

A Novel Software-Defined Convolutional Neural Networks Accelerator

The convolutional neural network (CNN) has been widely applied in computer vision applications. Due to the intensive computation, the general central processing unit (CPU) processors are not efficient to meet the real-time requirement. Various hardware accelerators based on the application specific integrated circuit (ASIC) and field programmable gate array (FPGA) have been designed to accelerate CNN models during the inference phase. The data flow architecture has been extensively adopted because of the high parallelism. However, given the continual development in the computer vision field, CNN models have become increasingly diverse. Thus, CNN accelerators based on data flow architectures face an emerging challenge to maintain high throughput while coping with various CNN models. In this paper, we design a software-defined architecture to solve this. The goal of this study is to make the hardware change as the application changes to achieve high flexibility and high performance. In our proposed architecture, all the parts can be software-defined to cope with different CNN models. A flexible software-defined processing element (PE) array is designed to compute different weight filter sizes. In addition, a software-defined data reuse technique based on two ideal reuse cases is proposed to ensure that all the parameters need to be loaded only once during the computing phase. To support this reuse technique, we also propose the software-defined on-chip buffer so that the weight and image buffers share one dynamic buffer. By using the sparsity property of the input feature map, the full-connected (FC) layer is accelerated. About 88% of the FC weight parameters can be skipped when loading the VGG-16 model. Finally, we implemented this software-defined accelerator on the FPGA. Compared to the other FPGA based accelerators, our proposed accelerator can preserve high performance while maintaining flexibility.

A Hardware and Software Task-Scheduling Framework Based on CPU+FPGA Heterogeneous Architecture in Edge Computing

Real-time performance is the primary requirement for edge computing systems. However, with the surge in data volume and the growing demand for computing power, a computing framework consisting solely of CPUs is no longer competent. As a result, CPU+ heterogeneous architecture using accelerators to improve edge computing systems' computing capacity has received great attention. The type of accelerators determines the performance of the edge computing system largely. The accelerators include Graphics Processing Unit (GPU), Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA). FPGAs with its reconfigurability and high energy efficiency are widely used in many edge computing scenarios. Nontheless, the performance depends also on the scheduling efficiency between software tasks on CPUs and hardware tasks on FPGAs. Unfortunately, the existing strategies have not fully exploited the differences between hardware and software tasks, thus resulting in low scheduling efficiency. This paper proposes a task scheduling framework on the Dynamic Partial Reconfiguration (DPR) platform. We take full account of the characteristics of task switching overhead and predictable execution time of hardware tasks in DPR, and reduce the number of task-switching times and active tasks in the system, thus improving the scheduling efficiency. We conduct a set of experiments on the Zynq platform to verify the proposed framework. Experimental results demonstrate that when the execution time of the accelerator exceeds the reconfiguration cost by an order of magnitude, the efficiencies of all the cases are more than 98%, and the efficiencies can reach 90%-98% in the same order of magnitude.

Rectifier Array With Adaptive Power Distribution for Wide Dynamic Range RF-DC Conversion

This paper presents a novel rectifier array for a wide dynamic range of RF-dc conversion. The rectifier array consists of multiple rectifier cells optimized for operation at different power levels and uses an adaptive power distribution method to divide the RF input power among these rectifier cells according to the RF power levels. The adaptive power distribution takes advantage of the power-dependent input impedances of the rectifier cells and is implemented with passive devices. This method both improves the rectification efficiency and minimizes the impedance mismatch as the input power level varies, and therefore, significantly enhances the dynamic range. The rectifier array can be designed using either the same type or different types of rectifying devices and can be expanded by including more cells in the network to further increase the dynamic range. In this paper, three different implementations of such rectifier array circuits are described, including a two-diode rectifier array designed with the same type of diodes, a two-diode rectifier array designed with different types of diodes, and a three-diode rectifier array with different types of diodes. The performances of these circuits are validated with measurement and compared with each other. Significant enhancement of dynamic range over conventional rectifiers is demonstrated.

Surrogate‐assisted design of microstrip corporate feeds integrated with linear microstrip array apertures for required sidelobe levels

AbstractA systematic computer‐aided design of low‐sidelobe linear microstrip antenna arrays is proposed. It starts from identifying the corporate feed architecture which is optimal for a given excitation taper under constrains imposed on the power splits within the feed. The novelty of the approach includes utilization of a numerically efficient simulation‐based kriging model of unequal split microstrip junctions for implementation of the optimal microstrip feed, and simulation‐based tuning of the excitation taper. The tuning is carried out with surrogate‐assisted optimization which is based on the electromagnetic simulations of an integrated array circuit comprising the aperture and the feed. Additionally, in‐phase excitation of the array aperture radiators is ensured with a simulation‐based correction of the corporate feed microstrip branches. The approach is implemented iteratively to realize the nominal sidelobe level. The approach is demonstrated with design of a 12‐element H‐plane 25‐dB sidelobe level Tschebyscheff array. Experimental validation is provided.

Mechanics Analysis and Hardware Implementation of a New 3D Chaotic System

In this study, a new 3D chaotic system was first transformed into a Kolmogorov-type system to describe the vector field from the viewpoint of torque. In this Kolmogorov-type system, only inertial torque and non-Rayleigh dissipation exist. Thus, this is different from previously reported Kolmogorov-type systems that are generally decomposed into inertial torque, internal torque, dissipation, and external torque. Moreover, by analyzing these two torques, the physical background of the system and the key factors of chaos generation were also determined. That is, the inertial torque and non-Rayleigh dissipation are responsible for chaos generation in the new 3D chaotic system. Then, the Casimir function and Hamiltonian energy function were also analyzed to investigate the cycling of energy in the chaotic system. Finally, both an analog circuit and a Field Programmable Gate Array (FPGA) circuit were designed to implement the chaotic system. All of the experimentally obtained results are consistent with the results of numerical analysis, which did not only indicate the chaotic characteristics of the 3D chaotic system physically, but also provided physical models for engineering applications.

Hardware implementation of the quasi‐maximum likelihood estimator core for polynomial phase signals

Flexible, multiple-clock-cycle, hardware design for the quasi-maximum likelihood (QML) algorithm core realisation for the polynomial phase signals (PPSs) estimation is proposed. The QML algorithm significantly outperforms existing PPS estimators in terms of accuracy. However, its practical applications require efficient software and hardware systems. The main challenges in the proposed hardware development with respect to existing systems for time–frequency (TF) analysis are realisation of TF representation based instantaneous frequency estimator, the polynomial regression, and phase extraction. The developed design is tested on a PPS corrupted by a white Gaussian noise and verified by a field programmable gate array circuit design. All implementation and verification details are provided along with the comparison of the results achieved by hardware and software implementations.

High-Throughput Pattern Matching With CMOL FPGA Circuits: Case for Logic-in-Memory Computing

In this paper, we propose a novel CMOS+MOLecular (CMOL) field-programmable gate array (FPGA) circuit architecture to perform massively parallel, high-throughput computations, which is especially useful for pattern matching tasks and multidimensional associative searches. In the new architecture, patterns are stored as resistive states of emerging nonvolatile memory nanodevices, while the analyzed data are streamed via CMOS subsystem. The main improvements over prior work offered by the proposed circuits are increased nanodevice utilization and, as a result, substantially higher throughput, which is demonstrated by a detailed analysis of the implementation of pattern matching task on the new architecture. For example, our estimates show that the proposed CMOL FPGA circuits based on the 22-nm CMOS technology and one crossbar layer with 22-nm nanowire half-pitch allows up to 12.5% average nanodevice utilization, i.e., the fraction of the devices turned to the high conductive state, as compared to a typical ~0.1% of the original CMOL FPGA circuits. This in turn enables throughput close to ${7.1\times 10^{16}}$ bits/s/cm2 at ~ 1 fJ/bit energy efficiency, for matching of ~ 107 250-bit patterns stored locally on a 1 cm2 chip. These numbers are at least 2 orders of magnitude better throughput as compared to that of other state-of-the-art FPGA methods, and begin to approach ternary content-addressable memory -like performance at similar CMOS technology nodes. More generally, we argue that the proposed concept combines the versatility of reconfigurable architectures and density of the associative memories. It can be viewed as a very tight symbiotic integration of memory and logic functions for high-performance logic-in-memory computing.

Initial operation results of NE213 scintillation detector for time-resolved measurements on triton burnup in KSTAR.

In time-resolved measurement for triton burnup in Korea Superconducting Tokamak Advanced Research (KSTAR) deuterium plasmas, an NE213 liquid scintillation detector was installed and operated during the 2017 KSTAR campaign. The detector is composed of an NE213 scintillator (50 mm in diameter and 10 mm in thickness) and a photomultiplier tube (PMT). The PMT anode signal was processed under a data acquisition system which contains a field programmable gate array circuit and pulse processing software that is capable of discriminating gamma-ray and neutron pulse signals. In order to determine an appropriate threshold level for the 14 MeV neutron signal resulting from triton burnup, the NE213 scintillation detector was calibrated by using d-d and d-t neutron generators at the National Fusion Research Institute and Intense 14 MeV Neutron Source Facility, OKTAVIAN, Osaka University, Japan. The detector was installed on KSTAR with a 10 mm thick soft-iron stray magnetic field shield and a radiation shield which consists of 100 mm thick lead blocks and 200 mm thick borated polyethylene blocks. A discrimination range for d-t neutron was determined based on test results from neutron generators and KSTAR. Data points selected from the discrimination range were consistent with the classical triton confinement characteristics. In conclusion, under condition of an input counting rate of 1.9 × 105 counts per second (CPS), the detector is able to measure triton burnup signals up to 500 CPS for various plasma parameters.