Abstract
Real-time performance is the primary requirement for edge computing systems. However, with the surge in data volume and the growing demand for computing power, a computing framework consisting solely of CPUs is no longer competent. As a result, CPU+ heterogeneous architecture using accelerators to improve edge computing systems' computing capacity has received great attention. The type of accelerators determines the performance of the edge computing system largely. The accelerators include Graphics Processing Unit (GPU), Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA). FPGAs with its reconfigurability and high energy efficiency are widely used in many edge computing scenarios. Nontheless, the performance depends also on the scheduling efficiency between software tasks on CPUs and hardware tasks on FPGAs. Unfortunately, the existing strategies have not fully exploited the differences between hardware and software tasks, thus resulting in low scheduling efficiency. This paper proposes a task scheduling framework on the Dynamic Partial Reconfiguration (DPR) platform. We take full account of the characteristics of task switching overhead and predictable execution time of hardware tasks in DPR, and reduce the number of task-switching times and active tasks in the system, thus improving the scheduling efficiency. We conduct a set of experiments on the Zynq platform to verify the proposed framework. Experimental results demonstrate that when the execution time of the accelerator exceeds the reconfiguration cost by an order of magnitude, the efficiencies of all the cases are more than 98%, and the efficiencies can reach 90%-98% in the same order of magnitude.
Highlights
With the surge in data volume, the growing demand for computing power and the increasing concern about safety, edge computing has received much attention in recent years
This paper proposes a scheduling method which deeply explores the characteristics of hardware task switching overhead and predictable execution time of hardware tasks in Dynamic Partial Reconfiguration (DPR) to improve scheduling efficiency of the whole system
Processing System (PS) with dual-core ARM Cortex-A9 is used as GPPs, and Programmable Logic (PL) with Xilinx 7 series programmable logic is used as Field Programmable Gate Array (FPGA) resources
Summary
With the surge in data volume, the growing demand for computing power and the increasing concern about safety, edge computing has received much attention in recent years. To solve the problems above, we propose a framework, which fully exploits the characteristic of hardware task switching and predictable execution time of hardware tasks in DPR, and reduces the task-switching frequency and the number of active tasks in the system, improving the scheduling efficiency. At the operating system (OS) level, this paper proposes a novel framework for task scheduling on DPR to reduce the context switch times and overhead. This paper proposes a scheduling method which deeply explores the characteristics of hardware task switching overhead and predictable execution time of hardware tasks in DPR to improve scheduling efficiency of the whole system. The proposed scheduling method can fully utilize the characteristics of hardware task cycle precision and non-preemption to reduce the task context switch times and overhead, improving the scheduling efficiency.
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