Partial Dynamic reconfiguration and task sceduling framework for FPGA: A survey with concepts, constraints and trends

Abstract

Generally the accelerators type identifies the edge computing performance hugely and it includes Integrated Circuit (IC), Graphical Processing Unit (GPU) and Field Programmable Gate Array (FPGA). Among these accelerator FPGAs are widely used in several edge computing areas since it has the ability to reconfigure and has high energy efficient. The consequence also comes out with the paradigm of scheduling efficiency on CPU’s (software tasks) and FPGA (hardware tasks). However the conventional schemes not entirely exploited the variations among hardware and software tasks which results in low scheduling efficiency. Therefore a task scheduling system is proposed on basis of fully active reconfigurable system. The scheduling efficiency for the proposed scheme can be increased by switching the task overheads and by predicting the execution time for hardware with minimum task switching times.