Exploiting the Dynamic Partial Reconfiguration on NoC-Based FPGA

Abstract

Dynamic Partial Reconfiguration (DPR) of SRAM-based Field Programmable Gate Arrays (FPGAs) becomes a demanding feature by many applications for its ability to add more flexibility over runtime phase. Recently, implementation designs which utilize DPR are easier than before. However, techniques that FPGAs use to perform DPR (like ICAP and JTAG) encounter a performance bottleneck; only one DPR is allowed at a time. In this paper, we present a state-of-art NoC-based FPGA simulator, which supports partial dynamic reconfiguration simulation. Design limitations and performance degradations of using DPR on NoC-based FPGA are estimated using NoC-DPR simulator. Experiments are carried out using NoC-DPR simulator to measure the reconfiguration time overhead by increasing number of simultaneous DPRs on FPGA fabric. It is shown that the overhead of reconfiguration time is increased exponentially with increasing the number of carried out simultaneous DPRs. However, DPR of NoC-based FPGA can enhance performance compared to DPR of normal FPGAs with some trade-offs.