Framework for Dynamic Partial Configuration of Algorithms for Zynq-7000 SoC using JPEG as Case Study

Abstract

The ability of the Field Programmable Gate Arrays (FPGAs) to reconfigure themselves makes them stand out and a preferred choice while designing an embedded system. The basic hardware architecture of FPGAs is the reason behind the availability of this unique feature. Most of the SRAM-based FPGAs supports partial reconfiguration (PR) feature. Many complex algorithms can be implemented using dynamic partial reconfiguration on FPGAs while occupying minimum possible area. Many applications implemented on FPGAs do not execute in a parallel fashion where different modules of the application are implemented over dedicated part of the hardware. Most of the time these modules are dependent on each other’s result therefore they cannot execute in parallel and leave a big amount of the FPGA area sitting idle most of the execution period. We propose a framework based on Dynamic partial reconfiguration, which allows scheduling the execution of multiple logic designs over the same area of FPGA fabric. In order to validate the proposed methodology, JPEG compression has been implemented as a case study Zynq-7000 SOC using both proposed framework and a single static implementation. In addition, the effectiveness of the proposed methodology is quantified by comparing the FPGA resource utilization of the original JPEG compression engine design and that of the partial re-configurable prototype. The results indicate a significant reduction in hardware resource utilization where 34%, 39% and 66% reduction has been achieved in Slice LUTs, Slice Registers and DSP blocks respectively.