ARM Cortex-M3 Research Articles

Benchmarking and Comparison of Two Open-source RTOSs for Embedded Systems Based on ARM Cortex-M4 MCU

Objective: To evaluate the performance of two open-source real-time operating systems (RTOSs), Keil RTX5 and FreeRTOS. Besides, a comparison between them has been also established based on four timing metrics: task switching time, pre-emption time, semaphore shuffling time, and inter-task messaging latency. All the tests have been performed on an STM32F429 discovery board based on Cortex-M4 MCUs. Methods: To measure the timing metrics, the ARM cycle counter register implemented in the DWT unit was used. Findings: The DWT cycle counter allows us to capture the number of cycles that occurred in the execution of a part of the code. Therefore, the time measurements of the metrics selected show that FreeRTOS has good performance with the lowest value of switching time, preemption time, and semaphore shuffling time. Instead, Keil RTX5 has fast message passing. Novelty: The study provides an evaluation and comparison of the latest version of the most used open-source RTOSs, Keil RTX5 and FreeRTOS v10.2.0. Furthermore, the timing metrics have been measured accurately with the ARM cycle counter register without using any other hardware or GPIO pin that may disturb the measurement. The comparison is based on four critical timing metrics that affect mostly the performance of any RTOS and define their time capability. Finally, the tests have been made on a low-power ARM MCU. Keywords: realtime operation system; embedded system; FreeRTOS; Keil RTX5; benchmarking metric; ARM MCU

A Side-Channel-Resistant Implementation of SABER

The candidates for the NIST Post-Quantum Cryptography standardization have undergone extensive studies on efficiency and theoretical security, but research on their side-channel security is largely lacking. This remains a considerable obstacle for their real-world deployment, where side-channel security can be a critical requirement. This work describes a side-channel-resistant instance of Saber, one of the lattice-based candidates, using masking as a countermeasure. Saber proves to be very efficient to masking due to two specific design choices: power-of-two moduli and limited noise sampling of learning with rounding. A major challenge in masking lattice-based cryptosystems is the integration of bit-wise operations with arithmetic masking, requiring algorithms to securely convert between masked representations. The described design includes a novel primitive for masked logical shifting on arithmetic shares and adapts an existing masked binomial sampler for Saber. An implementation is provided for an ARM Cortex-M4 microcontroller, and its side-channel resistance is experimentally demonstrated. The masked implementation features a 2.5x overhead factor, significantly lower than the 5.7x previously reported for a masked variant of NewHope. Masked key decapsulation requires less than 3,000,000 cycles on the Cortex-M4 and consumes less than 12kB of dynamic memory, making it suitable for deployment in embedded platforms.

Lock-V: A heterogeneous fault tolerance architecture based on Arm and RISC-V

This article presents Lock-V, a heterogeneous fault tolerance architecture that explores a dual-core lockstep (DCLS) technique to mitigate single event upset (SEU) and common-mode failure (CMF) problems. The Lock-V was deployed in two versions, Lock-VA and Lock-VM by applying design diversity in two processor architectures at the instruction set architecture (ISA)-level. Lock-VA features an Arm Cortex-A9 with a RISC-V RV64GC, while Lock-VM includes an Arm Cortex-M3 along with a RISC-V RV32IMA processor. The solution explores field-programmable gate array (FPGA) technology to deploy softcore versions of the RISC-V processors, and dedicated accelerators for performing error detection and triggering the software rollback system used for error recovery. To test Lock-V in both versions, a fault-injection mechanism was implemented to cause bit-flips in the processor registers, a common problem usually present in heavy radiation environments.

On the Functional and Extra-Functional Properties of IMU Fusion Algorithms for Body-Worn Smart Sensors.

In this work, four sensor fusion algorithms for inertial measurement unit data to determine the orientation of a device are assessed regarding their usability in a hardware restricted environment such as body-worn sensor nodes. The assessment is done for both the functional and the extra-functional properties in the context of human operated devices. The four algorithms are implemented in three data formats: 32-bit floating-point, 32-bit fixed-point and 16-bit fixed-point and compared regarding code size, computational effort, and fusion quality. Code size and computational effort are evaluated on an ARM Cortex M0+. For the assessment of the functional properties, the sensor fusion output is compared to a camera generated reference and analyzed in an extensive statistical analysis to determine how data format, algorithm, and human interaction influence the quality of the sensor fusion. Our experiments show that using fixed-point arithmetic can significantly decrease the computational complexity while still maintaining a high fusion quality and all four algorithms are applicable for applications with human interaction.

XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V Based IoT End Nodes

Heavily quantized fixed-point arithmetic is becoming a common approach to deploy Convolutional Neural Networks (CNNs) on limited-memory low-power IoT end-nodes. However, this trend is narrowed by the lack of support for low-bitwidth in the arithmetic units of state-of-the-art embedded Microcontrollers (MCUs). This work proposes a multi-precision arithmetic unit fully integrated into a RISC-V processor at the micro-architectural and ISA level to boost the efficiency of heavily Quantized Neural Network (QNN) inference on microcontroller-class cores. By extending the ISA with nibble (4-bit) and crumb (2-bit) SIMD instructions, we show near-linear speedup with respect to higher precision integer computation on the key kernels for QNN computation. Also, we propose a custom execution paradigm for SIMD sum-of-dot-product operations, which consists of fusing a dot product with a load operation, with an up to 1.64 × peak MAC/cycle improvement compared to a standard execution scenario. To further push the efficiency, we integrate the RISC-V extended core in a parallel cluster of 8 processors, with near-linear improvement with respect to a single core architecture. To evaluate the proposed extensions, we fully implement the cluster of processors in GF22FDX technology. QNN convolution kernels on a parallel cluster implementing the proposed extension run 6 × and 8 × faster when considering 4- and 2-bit data operands, respectively, compared to a baseline processing cluster only supporting 8-bit SIMD instructions. With a peak of 2.22 TOPs/s/W, the proposed solution achieves efficiency levels comparable with dedicated DNN inference accelerators and up to three orders of magnitude better than state-of-the-art ARM Cortex-M based microcontroller systems such as the low-end STM32L4 MCU and the high-end STM32H7 MCU.

Flight Control System Design and Autonomous Flight Control of Small-Scale Unmanned Helicopter Based on Nanosensors

Due to the limitation of the size and power, micro unmanned aerial vehicle (MUAV) usually has a small load capacity. Aiming at the problems of limited installation space and easy being interfered in flight attitude measurement of the small-scale unmanned helicopter (SUH), a low-cost and lightweight flight control system of the SUH based on ARM Cortex-M4 core microcontroller and Micro-Electro-Mechanical Systems (MEMS) sensors is developed in this paper. On this basis, in order to realize the autonomous flight control of SUH, firstly, the mathematical model of the SUH is given by using the Newton-Euler formulation. Secondly, a cascade flight controller consisting of the attitude controller and the position controller is developed based on linear active disturbance rejection control (LADRC) and proportional-integral-derivative (PID) control. Furthermore, simulations are conducted to validate the performance of the attitude controller and the position controller in MATLAB/SIMULINK simulation environment. Finally, based on the Align T-REX 470L SUH experimental platform, the hovering experiment and the route flight experiment are also carried out to validate the performance of the designed flight control system hardware and the proposed control algorithm. The results show that the flight control system designed in this paper has high reliability and strong anti-interference ability, and the control algorithm can effectively and reliably realize the attitude stabilization control and route control of the SUH, with high control accuracy and small error.

Simulation and experimental validation of hysteresis current control technique for speed control of brushless DC motor

Brushless DC Motors (BLDC) are finding wide applications in household appliances and electrical vehicles. Microcontroller are widely used for controlling the BLDC motors however the realization of BLDC drive requires expertise in microcontroller programming. In this paper modelling, simulation and easy hardware implementation of BLDC motor having shaft encoder using STM32F4 series ARM Cortex-M4 microcontroller is demonstrated. A simple method of controlling the BLDC motor in closed loop, using a hysteresis current controller is implemented. The hall sensors are used to find the exact rotor position for the electronic commutation and the encoder is used to measure actual motor speed. The closed loop operation consists of an inner loop which is hysteresis current controller. The gate pulses for the three phase inverter bridge are produced by comparing the actual currents with the reference currents. The outer speed loop consists of a PI controller which compares the actual speed with the reference speed to obtain smooth speed control under varied load condition. The complete hardware circuits and MATLAB/Simulink environment blocks for programming are discussed in detail. The hardware results demonstrate the easy and accurate realisation of closed loop speed control of BLDC Motor.

Quiescent photonics side channel analysis: Low cost SRAM readout attack

Optical emissions from semiconductors have been found to leak important information from embedded security devices. Unfortunately, the required substrate thinning and photon emission microscopy equipment is typically very expensive. Low cost equipment setups are proposed for substrate thinning/polishing and photon emission microscopy. For the first time, a security attack enabling the parallel readout of embedded SRAM while freezing the clock during any/all clock cycles is demonstrated to be viable on several embedded processors. In addition, quiescent photon emissions are shown to reveal the flash outputs. The quiescent photonics side channel attack is demonstrated on the PIC16F6xx family; in addition, quiescent emissions differential image analysis is demonstrated on an ARM Cortex-M0 device to reveal data-dependent emissions. This research has important security implications illustrating that the quiescent photonics side channel is a real threat for many embedded systems, especially lidless flipchips.

Upgradation of grid-connected water pumping system integrating multifunction PV inverter with reduced sensor

This article presents upgradation of existing grid-connected direct online-start water pumping system by integration of multifunction photovoltaic inverter. The multifunction photovoltaic inverter is operated using a voltage-oriented control such that it delivers the reactive power in addition to the real solar photovoltaic power to deal with practical issues like steady-state grid voltage variation and poor power factor on irrigation feeder. In the implemented voltage-oriented control, the adaptive modified second-order generalized integrator-based estimators are used to derive the grid voltage angle and the reactive component of the load current, which considerably reduces the requirement of the sensors. The methods to derive the different control system tuning parameters, i.e., second-order generalized integrator gains and proportional integral controller gains, are also described. A prototype is developed to investigate the performance of designed system. In the prototype, the control algorithm is implemented using a generic ARM Cortex-M4 microcontroller. Extensive experiments are performed, and the test results are presented to validate the system operations.

Virtual Laboratory for Studying and Programming Stm32 Microcontrollers

Currently, the design of platforms based on microcontrollers is a very promising direction due to their reduction in cost and increase in the performance of circuits. Microcontrollers are installed in industrial equipment, smartphones and audio players, video equipment, and much more. The paper provides the theoretical foundations for working with microcontrollers of the STM32 series, their purpose, system architecture, software model, as well as the features of the ARM Cortex M3 core. 32-bit core has many advantages, but the main one is its versatility. The structure of a software and hardware complex for studying and programming microcontrollers located on a remote server using the step-by-step debugging mode is described. The paper also discusses the features of writing programs for microcontrollers of the STM32 series. The virtual laboratory is a platform for the visual study of microcontrollers and the Assembler programming language. The system allows you to program, flash and debug microcontrollers without purchasing them. The user can test a code on a real device and view memory areas, registers and other debugging information in real time, as well as watch all changes in peripheral devices using video broadcast. The GDB GUI web interface allows you not to install additional applications, but to debug the program right in the browser. All kinds of sensors and indicators can be connected to the system, with which the user can work. Examples of programs written in the Assembler programming language are given to demonstrate the work of a virtual laboratory. The proposed platform can be integrated into a training course for learning the Assembler programming language.

Exploring Cortex-M Microarchitectural Side Channel Information Leakage

The growing Internet of Things (IoT) market demands side-channel attack resistant, efficient, cryptographic implementations. Such implementations, however, are microarchitecture-specific, and cannot be implemented without an in-depth structural knowledge of the CPU and memory information leakage patterns; a description of such information leakages is presently not disclosed by any processor design company. In this work we propose the first Instruction Set Architecture (ISA) level framework for microarchitectural leakage characterization. Our framework allows to extract a microarchitectural leakage profile from any superscalar in-order processor; we infer detailed pipeline characteristics through the observation of instruction timings, and provide an identification of the datapath registers via a side-channel measuring setup. The extracted model can serve as a foundation for building solid countermeasures against side-channel attacks on software cryptographic implementations. We validate the extracted models on the ARM Cortex-M4 and ARM Cortex-M7 CPUs, the latter being the most powerful CPU of the ARM microcontrollers offer. Finally, as a further demonstration of our model’s accuracy, we mount a successful attack on unprotected AES implementations for each of the examined platforms.

PRIMER: Profiling Interrupts using Electromagnetic Side-Channel for Embedded Devices

Recent proliferation of CPS and IoT devices has led to an increasing demand for analyzing performance and timing of event-driven computational activity, especially interrupts and exceptions. However, these devices typically lack hardware resources, power, and system-software infrastructure for profiling/monitoring such events. Even when feasible, the profiling/monitoring activity itself can perturb the performance and timing of the timing-sensitive activity to be analyzed, therefore producing misleading results. Thus, we present PRIMER, a novel approach for profiling interrupts. PRIMER leverages existing unintentional (side-channel) electromagnetic emanations of the profiled/monitored device to identify its asynchronous execution (e.g., interrupt handlers). PRIMER leaves the monitored system (and its behavior) completely unchanged, requires no system resources or support, and introduces neither overheads nor perturbation in the monitored system. We validate PRIMER by analyzing signals that correspond to five different types of interrupts on an IoT device (ARM Cortex-M), achieving 99.5% accuracy (with no false positives), and on an MSP430 microcontroller-based device with even better accuracy. We also demonstrate the effectiveness of PRIMER in analyzing page faults and network interrupts when executing real-world applications on a more sophisticated embedded device (ARM Cortex-A8), and show that the results provided by PRIMER can provide useful insights about an application's interaction with the system's virtual memory and network-oriented services.

Finding the Needle in the Haystack: Metrics for Best Trace Selection in Unsupervised Side-Channel Attacks on Blinded RSA

For asymmetric ciphers, such as RSA and ECC, side-channel attacks on the underlying exponentiation are mitigated by countermeasures like constant-time implementation and blinding. This restricts an attacker to a single side-channel trace for an attack as a different representation of the private key is used for each exponentiation. In this work, we propose an unsupervised machine learning framework for side-channel attacks on asymmetric cryptography that analyzes leakage in multiple side-channel traces, identifying the best trace for key retrieval. We apply Principal Component Analysis (PCA) preprocessing followed by a classification step that assigns segments of traces to elementary operations of the Square and Multiply exponentiation of RSA. In order to estimate the attack complexity for each trace in terms of key enumeration effort, we introduce two new metrics: The Entropy-based Cost Function (EBCF) is used to select a trace for the attack as well as bits which have to be brute-forced if not all bits can be determined correctly from this single trace. To reduce brute-force complexity further, we introduce Illegal Sequence Detection (ISD) to remove brute-force candidates which do not fit to the Square-and-Multiply scheme. We first provide a proof of concept for 320-bit key length traces and, moving towards a more realistic scenario, retrieve the key from a 1024-bit RSA implementation protected by message and exponent blinding. We are able to select the trace with the least remaining brute-force complexity from 1000 power measurements of the signature generation with randomized inputs and blinding values on a 32-bit ARM Cortex-M4 microcontroller.

An Efficient im2row-Based Fast Convolution Algorithm for ARM Cortex-M MCUs

With the rise of IoT and edge computing, deploying neural networks (NNs) on low-power edge computing devices is drawing more and more attention. In NNs, convolutional layers take up the majority of the computing cycles, especially when NNs are implemented on ARM processors [1]. Therefore, it is necessary to optimize the convolutional implementation on ARM Cortex-M MCUs. This paper proposes an efficient im2row-based fast convolution algorithm with two innovations. First, a novel im2row method for reusing the data of adjacent convolutional windows is presented. This method utilizes a reusable im2row buffer for data reuse, significantly reducing the amount of data copied during im2row and improving efficiency. Second, in algorithm implementation, a q7_t to q15_t data type extension technique that avoids data reordering is employed. This technique eliminates data reordering instructions, thus reducing the runtime of the algorithm. We evaluate our algorithm in separate convolutional layers and NNs. The results for convolutional layers show that, compared to baseline, the proposed algorithm speeds up the convolutional layer by an average of 1.42x, and the maximum speedup is up to 2.9x. Experiments on different NNs demonstrate that our algorithm can speed up the overall NN by up to 2.15x.

Singular Value Decomposition in Embedded Systems Based on ARM Cortex-M Architecture

Singular value decomposition (SVD) is a central mathematical tool for several emerging applications in embedded systems, such as multiple-input multiple-output (MIMO) systems, data analytics, sparse representation of signals. Since SVD algorithms reduce to solve an eigenvalue problem, that is computationally expensive, both specific hardware solutions and parallel implementations have been proposed to overcome this bottleneck. However, as those solutions require additional hardware resources that are not in general available in embedded systems, optimized algorithms are demanded in this context. The aim of this paper is to present an efficient implementation of the SVD algorithm on ARM Cortex-M. To this end, we proceed to (i) present a comprehensive treatment of the most common algorithms for SVD, providing a fairly complete and deep overview of these algorithms, with a common notation, (ii) implement them on an ARM Cortex-M4F microcontroller, in order to develop a library suitable for embedded systems without an operating system, (iii) find, through a comparative study of the proposed SVD algorithms, the best implementation suitable for a low-resource bare-metal embedded system, (iv) show a practical application to Kalman filtering of an inertial measurement unit (IMU), as an example of how SVD can improve the accuracy of existing algorithms and of its usefulness on a such low-resources system. All these contributions can be used as guidelines for embedded system designers. Regarding the second point, the chosen algorithms have been implemented on ARM Cortex-M4F microcontrollers with very limited hardware resources with respect to more advanced CPUs. Several experiments have been conducted to select which algorithms guarantee the best performance in terms of speed, accuracy and energy consumption.

Evaluation of Different Processor Architecture Organizations for On-Site Electronics in Harsh Environments

Microcontrollers to be used in harsh environmental conditions, e.g., at high temperatures or radiation exposition, need to be fabricated in robust technology nodes in order to operate reliably. However, these nodes are considerably larger than cutting-edge semiconductor technologies and provide less speed, drastically reducing system performance. In order to achieve low silicon area costs, low power consumption and reasonable performance, the processor architecture organization itself is a major influential design point. Parameters like data path width, instruction execution paradigm, code density, memory requirements, advanced control flow mechanisms etc., may have large effects on the design constraints. Application characteristics, like exploitable data parallelism and required arithmetic operations, have to be considered in order to use the implemented processor resources efficiently. In this paper, a design space exploration of five different architectures with MIPS- or ARM-compatible instruction set architectures, as well as transport-triggered instruction execution is presented. Using a 0.18 upmu m SOI CMOS technology for high temperature and an exemplary case study from the fields of communication, i.e., powerline communication encoder, the influence of architectural parameters on performance and hardware efficiency is compared. For this application, a transport-triggered architecture configuration has an 8.5times higher performance and 2.4times higher computational energy efficiency at a 1.6times larger total silicon area than an off-the-shelf ARM Cortex-M0 embedded processor, showing the considerable range of design trade-offs for different architectures.

A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low Power Applications

Design of high-performance processors with very low power requirement is the primary goal of many contemporary and futuristic applications. This brief presents a novel processor micro-architecture which is capable of achieving these requirements. The micro-architecture is based on RISC-V Instruction Set Architecture (ISA). The core is implemented and verified on Xilinx Virtex-7 FPGA board with a resource requirement of 7617 LUTs and 2319 FFs. This core could achieve a Dhrystone benchmark score of 1.71 DMIPS per MHz which is higher than ARM Cortex-M3 (1.50 DMIPS per MHz) and ARM Cortex-M4 (1.52 DMIPS per MHz). The Coremark benchmark is also tested on this core and it gives 4.13 Coremark per MHz. The physical design result of the core using commercial tools shows that it can achieve a maximum frequency of 198.02 MHz with 0.036 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area and 17.36 μW/MHz power requirement at UMC 40 nm technology node. The core consumes a dynamic power of 19.75 μW/MHz at UMC 90nm which is 36% and 40% better than ARM Cortex-M3 and Cortex-M4 respectively and also lower than many others cores. The results show that this core can outperform many existing commercial and open-source cores.

A blockchain-based architecture for secure and trustworthy operations in the industrial Internet of Things

The industrial Internet of Things (IIoT) plays an important role in the industrial sector, where secure, scalable, and easily adopted technologies are being implemented for the smart industry. The traditional IIoT architectures are generally based on centralized architectures that are vulnerable to a single point of failure and to several cyber-attacks. Blockchain technology is frequently adopted in the modern industry because of its security and decentralization. This paper proposes a blockchain-based architecture that ensures secure and trustworthy industrial operations. A private and lightweight blockchain architecture is proposed to regulate access to valuable sensor and actuator data. To enhance the computational performance of the proposed architecture, real-time cryptographic algorithms are processed using a low-power ARM Cortex-M4 processor, and a highly scalable, fast, and energy-efficient consensus mechanism proof of authentication (PoAh) is deployed in the blockchain network. Extensive experiments and analysis proved the effectiveness of the proposed framework for smart industrial environments. Finally, we transform a conventional fruit processing plant into a secure and smart industrial platform by implementing the proposed architecture.

Rapidly Verifiable XMSS Signatures

This work presents new speed records for XMSS (RFC 8391) signature verification on embedded devices. For this we make use of a probabilistic method recently proposed by Perin, Zambonin, Martins, Custódio, and Martina (PZMCM) at ISCC 2018, that changes the XMSS signing algorithm to search for rapidly verifiable signatures. We improve the method, ensuring that the added signing cost for the search is independent of the message length. We provide a statistical analysis of the resulting verification speed and support it by experiments. We present a record setting RFC compatible implementation of XMSS verification on the ARM Cortex-M4. At a signing time of about one minute on a general purpose CPU, we create signatures that are verified about 1.44 times faster than traditionally generated signatures. Adding further well-known implementation optimizations to the verification algorithm we reduce verification time by over a factor two from 13.85 million to 6.56 million cycles. In contrast to previous works, we provide a detailed security analysis of the resulting signature scheme under classical and quantum attacks that justifies our selection of parameters. On the way, we fill a gap in the security analysis of XMSS as described in RFC 8391 proving that the modified message hashing in the RFC does indeed mitigate multi-target attacks. This was not shown before and might be of independent interest.

Fixslicing AES-like Ciphers

The fixslicing implementation strategy was originally introduced as a new representation for the hardware-oriented GIFT block cipher to achieve very efficient software constant-time implementations. In this article, we show that the fundamental idea underlying the fixslicing technique is not of interest only for GIFT, but can be applied to other ciphers as well. Especially, we study the benefits of fixslicing in the case of AES and show that it allows to reduce by 52% the amount of operations required by the linear layer when compared to the current fastest bitsliced implementation on 32-bit platforms. Overall, we report that fixsliced AES-128 allows to reach 80 and 91 cycles per byte on ARM Cortex-M and E31 RISC-V processors respectively (assuming pre-computed round keys), improving the previous records on those platforms by 21% and 26%. In order to highlight that our work also directly improves masked implementations that rely on bitslicing, we report implementation results when integrating first-order masking that outperform by 12% the fastest results reported in the literature on ARM Cortex-M4. Finally, we demonstrate the genericity of the fixslicing technique for AES-like designs by applying it to the Skinny-128 tweakable block ciphers.