Abstract
The growing Internet of Things (IoT) market demands side-channel attack resistant, efficient, cryptographic implementations. Such implementations, however, are microarchitecture-specific, and cannot be implemented without an in-depth structural knowledge of the CPU and memory information leakage patterns; a description of such information leakages is presently not disclosed by any processor design company. In this work we propose the first Instruction Set Architecture (ISA) level framework for microarchitectural leakage characterization. Our framework allows to extract a microarchitectural leakage profile from any superscalar in-order processor; we infer detailed pipeline characteristics through the observation of instruction timings, and provide an identification of the datapath registers via a side-channel measuring setup. The extracted model can serve as a foundation for building solid countermeasures against side-channel attacks on software cryptographic implementations. We validate the extracted models on the ARM Cortex-M4 and ARM Cortex-M7 CPUs, the latter being the most powerful CPU of the ARM microcontrollers offer. Finally, as a further demonstration of our model’s accuracy, we mount a successful attack on unprotected AES implementations for each of the examined platforms.
Highlights
E MBEDDED and Internet of Things (IoT) industries commonly use cryptographic algorithms to guarantee authenticity on data retrieved from remote devices, integrity on firmware updates delivered to said devices, and confidentiality on data transmitted via radio channels
The model is simulated for all the possible values of a secret portion, e.g., the first byte of the secret key, and the correct hypothesis will be the one with the higher correlation between the sidechannel model and the sampled values; this attack is known as Correlation Power Analysis (CPA)
This phenomenon is the consequence of the presence of registers in the datapath of pipelined processors; as Balasch et al detailed in their work [17], register transitions generate a leakage that is proportional to the Hamming Distance (HD) of the previous and the new value
Summary
E MBEDDED and Internet of Things (IoT) industries commonly use cryptographic algorithms to guarantee authenticity on data retrieved from remote devices, integrity on firmware updates delivered to said devices, and confidentiality on data transmitted via radio channels. As Barenghi et al demonstrated [17, 18], a microarchitecture might leak the combination of two shares, even if at Instruction Set Architecture (ISA) level the two shares are not explicitly mixed, e.g., through register reuse or Arithmetic Logic Unit (ALU) operations This phenomenon is the consequence of the presence of registers in the datapath of pipelined processors; as Balasch et al detailed in their work [17], register transitions generate a leakage that is proportional to the Hamming Distance (HD) of the previous and the new value. Through the execution of a set of ad-hoc microbenchmarks, and the measurement of softwareonly parameters such as execution latency, throughput and physical phenomena (i.e., EM emissions), is able to yield a structural characterization of the side-channel relevant features of a target processor and memory subsystem, such as the size and location of all the datapath synchronous registers, and the microarchitectural features necessary to correctly model their leakage behaviors. This work represents a first systematic attempt to derive a leakage model that, can be practically used to derive CPAresistant software implementations, and to gain in-depth knowledge about the causes of the observed leakage, contrarily to many data-driven approaches, which are unable to track down the causes of the observed leakage phenomena
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