ARM Cortex-M3 Research Articles

Design, analysis and implementation of electronically interfaced photovoltaic system using ARM Cortex-M4 microcontroller

This research article presents a detailed documentation regarding test-bench development of Grid Interfaced Solar Photovoltaic (GIPV) system. The proposed GIPV system is developed using Voltage Source Converter (VSC) and DC-DC boost converter. The GIPV test-bench is developed using various auxiliary circuits including voltage/current measuring circuit, signal conditioning circuit, phase-shifting circuit, complementary pulse generation circuit, and driver circuit etc. These auxiliary circuits are designed in express printed circuit board software and fabricated in laboratory to develop a complete GIPV system test-bench. A combination of modified Synchronous Reference Frame (SRF) scheme and Proportional Resonant (PR) controller is proposed for current reference generation. Amplitude adaptivity based SRF-Phase Locked Loop (SRF-PLL) is presented to precisely detect the phase-angle of grid voltage under distorted and unbalanced conditions. The prototype is implemented using a commercially cheap ARM Cortex-M4 based STM32F407VGT6 microcontroller. This microcontroller has diversified peripherals for flexible target set-up with faster computation capability and a sophisticated user interface having TCP/IP connectivity. The control structure is developed in waijung environment for automatic code generation. The effectiveness of the proposed control algorithm is tested by numerical simulations in MATLAB/Simulink. Finally, practicality of the proposed GIPV system is experimentally demonstrated using ARM based microcontroller under various operating conditions.

TinyML-Based Concept System Used to Analyze Whether the Face Mask Is Worn Properly in Battery-Operated Conditions

As the COVID-19 pandemic emerged, everyone’s attention was brought to the topic of the health and safety of the entire human population. It has been proven that wearing a face mask can help limit the spread of the virus. Despite the enormous efforts of people around the world, there still exists a group of people that wear face masks incorrectly. In order to provide the best level of safety for everyone, face masks must be worn correctly, especially indoors, for example, in shops, cinemas and theaters. As security guards can only handle a limited area of the frequently visited objects, intelligent sensors can be used. In order to mount them on the shelves in the shops or near the cinema cash register queues, they need to be capable of battery operation. This restricts the sensor to be as energy-efficient as possible, in order to prolong the battery life of such devices. The cost is also a factor, as cheaper devices will result in higher accessibility. An interesting and quite novel approach that can answer all these challenges is a TinyML system, that can be defined as a combination of two concepts: Machine Learning (ML) and Internet of Things (IoT). The TinyML approach enables the usage of ML algorithms on boards equipped with low-cost, low-power microcontrollers without sacrificing the classifier quality. The main goal of this paper is to propose a battery-operated TinyML system that can be used for verification whether the face mask is worn properly. To this end, we carefully analyze several ML approaches to find the best method for the considered task. After detailed analysis of computation and memory complexity as well as after some preliminary experiments, we propose to apply the K-means algorithm with carefully designed filters and a sliding window technique, since this method provides high accuracy with the required energy-efficiency for the considered classification problem related to verification of using the face mask. The STM32F411 chip is selected as the best microcontroller for the considered task. Next, we perform wide experiments to verify the proposed ML framework implemented in the selected hardware platform. The obtained results show that the developed ML-system offers satisfactory performance in terms of high accuracy and lower power consumption. It should be underlined that the low-power aspect makes it possible to install the proposed system in places without the access to power, as well as reducing the carbon footprint of AI-focused industry which is not negligible. Our proposed TinyML system solution is able to deliver very high-quality metric values with accuracy, True Positive Ratio (TPR), True Negative Ratio (TNR), precision and recall being over 96% for masked face classification while being able to reach up to 145 days of uptime using a typical 18650 battery with capacity of 2500 mAh and nominal voltage of 3.7 V. The results are obtained using a STM32F411 microcontroller with 100 MHz ARM Cortex M4, which proves that execution of complex computer vision tasks is possible on such low-power devices. It should be noted that the STM32F411 microcontroller draws only 33 mW during operation.

Optimized Implementation of PIPO Block Cipher on 32-Bit ARM and RISC-V Processors

A lightweight block cipher PIPO-64/128 was presented in ICISC’2020. PIPO of the 8-bit unit using an unbalanced-bridge S-box showed better performance than other lightweight block cipher algorithms on an 8-bit AVR environment. So far, optimization methods for implementing PIPO have been proposed in various environments; however, no optimization research has been conducted for two popular 32-bit based processors: ARM Cortex-M4 and RISC-V. Since RISC-V and ARM Cortex-M series platforms do not support bit-based Single Instruction Multiple Data (SIMD) instructions, several aspects should be considered to apply a forced parallelization strategy. In this article, we discuss the implementation methodology of PIPO for 32-bit RISC-V and ARM Cortex-M4 environments. We optimize the performance of S-Layer via proposed register-scheduling and masking technique while we maintain parallelism to the R-Layer implementation. Moreover, we propose an on-the-fly key scheduling technique for further performance improvement. Finally, compared to the existing reference implementations in RISC-V and ARM Cortex-M4 platforms, when 4 plaintext encrypted simultaneously, our software achieved performance of 229% and 370%, respectively.

Accelerating Falcon on ARMv8

Falcon is one of the promising digital-signature algorithms in NIST’s ongoing Post-Quantum Cryptography (PQC) standardization finalist. Computational efficiency regarding software and hardware is also the main criteria for PQC standardization. In this paper, we present an efficient Falcon software implementation on ARMv8 environment. Until now, most of the software optimization on PQC algorithms have been conducted on 32-bit ARM (Cortex-M4) and typical CPUs (Intel and AMD CPUs). However, ARMv8 including Cortex-A30, 50, and 70 series have been widely used for various IoT (Internet of Things) applications, Edge computing devices, and OBUs (On Board Units) in autonomous driving cars. For optimizing the performance of Falcon, we take full advantage of NEON engine which is a kind of parallel processing unit in ARMv8 MCU. The main computation in Falcon belongs to polynomial multiplications in Complex number domain and Integer domain. Typically, FFT (Fast Fourier Transformation)-based multiplication method and NTT (Number Theoriteic Transform)-based multiplication method have been widely used for efficient polynomial multiplications in Complex number domain and Integer domain, respectively. Thus, in order to enhance the overall performance of Falcon, we improve the FFT-based multiplication method and NTT-based multiplication method by utilizing NEON engine in ARMv8. Specifically, we parallelize the overall process (FFT/NTT transformation, pointwise multiplication, and inverse FFT/NTT transformation) of FFT-based polynomial multiplication method and NTT-based polynomial multiplication method with strategically utilizing the NEON engine and vector instructions. Furthermore, we minimize the number of redundant memory accesses during FFT/NTT-based polynomial multiplication by making the most of available registers in NEON engine. Through the proposed parallel FFT/NTT-based polynomial multiplications, the proposed Falcon software provides 15.1% (resp. 18.1%), 16.5% (resp. 17.1%), and 65.4% (resp. 69.4%) of performance improvement in keypair generation, signing, and verification at security level 1 (resp. 5) compared with the reference Falcon implementation submitted to the final round of NIST PQC competition. Furthermore, as far as we know, this is the first optimized implementation of Falcon on ARMv8 environment.

Design and Performance Evaluation of an Ultralow-Power Smart IoT Device With Embedded TinyML for Asset Activity Monitoring

This article proposes a proof-of-concept device to continuously assess the usage of handheld power tools and detect construction working tasks (e.g., different drilling works) along with potential misusages, e.g., drops, with an energy-efficient architecture design. The designed device is based on Bluetooth low energy (BLE) and NFC connectivity. BLE is used to exchange data with a gateway, whereas NFC has been chosen as an energy-efficient wake-up mechanism. A temperature and humidity sensor is embedded to monitor storage conditions and an accelerometer for tool usage monitoring. The ARM Cortex-M4 core embedded in the BLE module is exploited to process the information at the edge. A Tiny Machine Learning (TinyML) algorithm is proposed to process the data directly on board and achieve low latency and high energy efficiency. The TinyML algorithm has been developed embedded in the proposed device to detect four different usage classes (tool transportation, no-load, metal, and wood drilling). A dataset containing more than 280 min of three-axis accelerations during different activities has been acquired with the device attached to a construction rotary hammer drill and used to train and validate the algorithm. A neural architecture search has been performed to optimize the trade-off between accuracy and complexity, achieving an accuracy of 90.6% with a model size of roughly 30 kB. The experimental results showed an ultralow power consumption in sleep mode of 550 nA and a peak power consumption of 8 mA while running TinyML on the edge. This results in a balanced combination of edge processing capabilities and low power consumption, enabling to obtain a smart Internet of Things (IoT) device in the field with a long lifetime of up to four years in operation and 17 years in shelf mode with a standard 250-mAh coin battery. This work enables a long battery lifetime operation of device degradation and utility analysis, further closing the gap between edge processing and fine granularity data evaluation.

Embedded AM-FM Signal Decomposition Algorithm for Continuous Human Activity Monitoring

AM-FM decomposition techniques have been successfully used for extracting significative features from a large variety of signals, helping realtime signal monitoring and pattern recognition, since they represent signals as a simultaneous composition of amplitude modulation and frequency modulation, where the carriers, amplitude envelopes, and the instantaneous frequencies are the features to be estimated. Human activities often involve repetitive movements, such as in running or cycling, where sinusoidal AM-FM decompositions of signals have already demonstrated to be useful to extract compact features to aid monitoring, classification, or detection. In this work we thus present the challenges and results of implementing the iterated coherent Hilbert decomposition (ICHD), a particularly effective algorithm to obtain an AM-FM decomposition, within a resource-constrained and low-power ARM Cortex-M4 microcontroller that is present in a wearable sensor we developed. We apply ICHD to the gyroscope data acquired from an inertial measurement unit (IMU) that is present in the sensor. Optimizing the implementation allowed us to achieve real-time performance using less then 16 % of the available CPU time, while consuming only about 5.4 mW of power, which results in a run-time of over 7 days using a small 250 mAh rechargeable cell.

Benchmarking of Symmetric Cryptographic Algorithms on a Deeply Embedded System

In this paper, we study the runtime performance of symmetric cryptographic algorithms on an embedded ARM Cortex-M4 platform. Symmetric cryptographic algorithms can serve to protect the integrity and optionally, if supported by the algorithm, the confidentiality of data. A broad range of well-established algorithms exists, where the different algorithms typically have different properties and come with different computational complexity. On deeply embedded systems, the overhead imposed by cryptographic operations may be significant. We execute the algorithms AES-GCM, ChaCha20-Poly1305, HMAC-SHA256, KMAC, and SipHash on an STM32 embedded microcontroller and benchmark the execution times of the algorithms as a function of the input lengths.

Electromagnetic failure analysis of control system processors in the internet of things

Control system processors in networked control systems are susceptible to malware attacks and failures. Monitoring stuck-at faults and malware at a distance is more resilient and can be integrated into frameworks for the Internet of Things. We offer a technique for failure/performance analysis based on the electromagnetic spectral domain that is completely decoupled from the controller processor. Without being a part of the monitored system, it can investigate failure causes on a complicated six-stage pipelined microarchitecture. Due to the fact that malware cannot traverse EM side-channels, our monitor is immune to controller-level malware attacks and can also work without requiring controller alteration. The traces were analysed using Support Vector Machines, AdaBoost, Quadratic Discriminant Analysis, Gaussian Process Classifiers, and Naive Bayes in the frequency domain. On a six-stage pipelined ARM Cortex-M7, our results demonstrated an accuracy of over 80% in predicting control system stuck-at errors and various types of malware.

Leveraging Tactile Sensors for Low Latency Embedded Smart Hands for Prosthetic and Robotic Applications

Tactile sensing is a crucial perception mode for robots and human amputees in need of controlling a prosthetic device. Today, robotic and prosthetic systems are still missing the important feature of accurate tactile sensing. This lack is mainly due to the fact that the existing tactile technologies have limited spatial and temporal resolution and are either expensive or not scalable. In this article, we present the design and implementation of a hardware–software embedded system called SmartHand. It is specifically designed to enable the acquisition and real-time processing of high-resolution tactile information from a hand-shaped multisensor array for prosthetic and robotic applications. During data collection, our system can deliver a high throughput of 100 frames per second, which is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$13.7\times $ </tex-math></inline-formula> higher than previous related work. This has allowed the collection of a new tactile dataset consisting of 340 000 frames while interacting with 16 objects from everyday life during five different sessions. Together with the empty hand, the dataset presents a total of 17 classes. We propose a compact yet accurate convolutional neural network that requires one order of magnitude less memory and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$15.6\times $ </tex-math></inline-formula> fewer computations compared with related work without degrading classification accuracy. The top-1 and top-3 cross-validation accuracies on the collected dataset are, respectively, 98.86% and 99.83%. We further analyze the intersession variability and obtain the best top-3 leave-one-out-validation accuracy of 77.84%. We deploy the trained model on a high-performance ARM Cortex-M7 microcontroller achieving an inference time of only 100 ms minimizing the response latency. The overall measured power consumption is 505 mW. Finally, we fabricate a new control sensor and perform additional experiments to provide analyses on sensor degradation and slip detection. This work is a step forward in giving robotic and prosthetic devices a sense of touch by demonstrating the practicality of a smart embedded system that uses a scalable tactile sensor with embedded tiny machine learning.

Design and Implementation of a Novel Intelligent Strategy for the Permanent Magnet Synchronous Motor Emulation

In this paper, an intelligent neural network‐based controller is designed and implemented to control the speed of a permanent magnet synchronous motor (PMSM). First, the exact mathematical model of PMSM is presented, and then, by designing a controller, we apply the wind turbine emulation challenges. The designed controller for the first time is implemented on a Arm Cortex‐M microcontroller and tested on a laboratory PMSM. Since online learning neural network on a chip requires a strong processor, high memory, and convergence guarantee, this article uses the offline method. In this method, first, for different work points, the neural network is trained by local controllers, and then, the trained network is implemented on the chip and used. Uncertainty in the parameters and the effect of load torque as challenges of control systems are applied in the proposed method, and a comparison with other methods is performed in the implementation results section.

Three-phase inverter with a variable control algorithm

The paper presents the construction of a three-phase frequency converter with the possibility of choosing the type of PWM modulation and a smooth change of the frequency of the modulated signal. In a practical way, various inverter control algorithms were implemented in the same hardware system using the STM ARM Cortex M3 processor. The use of THIPWM modulation allowed to reduce the harmonic content in the output signal and effectively use the possibilities of the power source. The system can choose one of two scalar control algorithms, with the option of compensation for the influence of the stator resistance on the motor shaft torque in the initial range of the linear control characteristic at a constant voltage to frequency ratio. The research confirmed that the most advantageous type of PWM in this system is unipolar double-edge modulation. The use of the THIPWM method resulted in a gain in the amplitude of the fundamental harmonic of the output voltage for the three-phase inverter operation mode compared to the SPWM method. The appropriate precision of the frequency control step was also obtained, and the test results confirmed the functionality of the converter.

Локальний web-сервер телеметричної системи з сенсорами взаємодії за протоколом modbus

With the development of microprocessor components and, accordingly, a significant expansion of the use of computer technologies, remote measurement techniques are being developed. These include telemetry and remote control of technical systems or their components in industry, research, home appliances and other fields. In this paper, the author suggests how to build a local web-server based on a microcontroller with an ARM Cortex-M4 core, which can be interacted with via an http-browser with Internet access. The block diagram of the local web-server on the basis of the STM32F407 microcontroller with the ARM Cortex-M4 core is suggested. Hardware modeling of the local web-server with a two-processor architecture including the main controller and the Modbus processor with the RS-485 interface, which provides information exchange via the Modbus RTU protocol, is done. The main controller is equipped with an indicator system based on functionally programmable LED indicators, an LCD indicator of type BC1602A, a local keyboard, USB and SWD ports for debugging and programming of the microcontroller, an external Ethernet module providing a temperature sensor and the Modbus RTU relay module, which interacts with the main controller of the local web-server via the Modbus processor with the RS-485 interface using the Modbus RTU protocol. A software for interaction of the local web-server and a http-browser has been developed. The local web-server was tested with different types of http browsers, proved to be reliable and showed the response time which depends on the number of sensors and is less than 1 second in case of 9 sensors.

A Finer-Grain Analysis of the Leakage (Non) Resilience of OCB

OCB3 is one of the winners of the CAESAR competition and is among the most popular authenticated encryption schemes. In this paper, we put forward a fine-grain study of its security against side-channel attacks. We start from trivial key recoveries in settings where the mode can be attacked with standard Differential Power Analysis (DPA) against some block cipher calls in its execution (namely, initialization, processing of associated data or last incomplete block and decryption). These attacks imply that at least these parts must be strongly protected thanks to countermeasures like masking. We next show that if these block cipher calls of the mode are protected, practical attacks on the remaining block cipher calls remain possible. A first option is to mount a DPA with unknown inputs. A more efficient option is to mount a DPA that exploits horizontal relations between consecutive input whitening values. It allows trading a significantly reduced data complexity for a higher key guessing complexity and turns out to be the best attack vector in practical experiments performed against an implementation of OCB3 in an ARM Cortex-M0. Eventually, we consider an implementation where all the block cipher calls are protected. We first show that exploiting the leakage of the whitening values requires mounting a Simple Power Analysis (SPA) against linear operations. We then show that despite being more challenging than when applied to non-linear operations, such an SPA remains feasible against 8-bit implementations, leaving its generalization to larger implementations as an interesting open problem. We last describe how recovering the whitening values can lead to strong attacks against the confidentiality and integrity of OCB3. Thanks to this comprehensive analysis, we draw concrete requirements for side-channel resistant implementations of OCB3.

Will You Cross the Threshold for Me?

In this work, we propose generic and novel side-channel assisted chosenciphertext attacks on NTRU-based key encapsulation mechanisms (KEMs). These KEMs are IND-CCA secure, that is, they are secure in the chosen-ciphertext model. Our attacks involve the construction of malformed ciphertexts. When decapsulated by the target device, these ciphertexts ensure that a targeted intermediate variable becomes very closely related to the secret key. An attacker, who can obtain information about the secret-dependent variable through side-channels, can subsequently recover the full secret key. We propose several novel CCAs which can be carried through by using side-channel leakage from the decapsulation procedure. The attacks instantiate three different types of oracles, namely a plaintext-checking oracle, a decryptionfailure oracle, and a full-decryption oracle, and are applicable to two NTRU-based schemes, which are NTRU and NTRU Prime. The two schemes are candidates in the ongoing NIST standardization process for post-quantum cryptography. We perform experimental validation of the attacks on optimized and unprotected implementations of NTRU-based schemes, taken from the open-source pqm4 library, using the EM-based side-channel on the 32-bit ARM Cortex-M4 microcontroller. All of our proposed attacks are capable of recovering the full secret key in only a few thousand chosen ciphertext queries on all parameter sets of NTRU and NTRU Prime. Our attacks, therefore, stress on the need for concrete side-channel protection strategies for NTRUbased KEMs.

Practical Multiple Persistent Faults Analysis

We focus on the multiple persistent faults analysis in this paper to fill existing gaps in its application in a variety of scenarios. Our major contributions are twofold. First, we propose a novel technique to apply persistent fault apply in the multiple persistent faults setting that decreases the number of survived keys and the required data. We demonstrate that by utilizing 1509 and 1448 ciphertexts, the number of survived keys after performing persistent fault analysis on AES in the presence of eight and sixteen faults can be reduced to only 29 candidates, whereas the best known attacks need 2008 and 1643 ciphertexts, respectively, with a time complexity of 250. Second, we develop generalized frameworks for retrieving the key in the ciphertext-only model. Our methods for both performing persistent fault attacks and key-recovery processes are highly flexible and provide a general trade-off between the number of required ciphertexts and the time complexity. To break AES with 16 persistent faults in the Sbox, our experiments show that the number of required ciphertexts can be decreased to 477 while the attack is still practical with respect to the time complexity. To confirm the accuracy of our methods, we performed several simulations as well as experimental validations on the ARM Cortex-M4 microcontroller with electromagnetic fault injection on AES and LED, which are two well-known block ciphers to validate the types of faults and the distribution of the number of faults in practice.

Low-complexity three-dimensional discrete Hartley transform approximations for medical image compression

The discrete Hartley transform (DHT) is a useful tool for medical image coding. The three-dimensional DHT (3D DHT) can be employed to compress medical image data, such as magnetic resonance and X-ray angiography. However, the computation of the 3D DHT involves several multiplications by irrational quantities, which require floating-point arithmetic and inherent truncation errors. In recent years, a significant progress in wireless and implantable biomedical devices has been achieved. Such devices present critical power and hardware limitations. The multiplication operation demands higher hardware, power, and time consumption than other arithmetic operations, such as addition and bit-shifts. In this work, we present a set of multiplierless DHT approximations, which can be implemented with fixed-point arithmetic. We derive 3D DHT approximations by employing tensor formalism. Such proposed methods present prominent computational savings compared to the usual 3D DHT approach, being appropriate for devices with limited resources. The proposed transforms are applied in a lossy 3D DHT-based medical image compression algorithm, presenting practically the same level of visual quality (>98% in terms of SSIM) at a considerable reduction in computational effort (100% multiplicative complexity reduction). Furthermore, we implemented the proposed 3D transforms in an ARM Cortex-M0+ processor employing the low-cost Raspberry Pi Pico board. The execution time was reduced by ∼70% compared to the usual 3D DHT and ∼90% compared to 3D DCT.

Ultra-low-power Physical Activity Classifier for Wearables: From Generic MCUs to ASICs.

In the era of Internet of Things (IoT), an increasing amount of sensors is being integrated into intelligent wearable devices. These sensors have the potential to produce a large quantity of physiological data streams to be analyzed in order to produce meaningful and actionable information. An important part of this processing is usually located in the device itself and takes the form of embedded algorithms which are executed into the onboard microcontroller (MCU). As data processing algorithms have become more complex due to, in part, the disruption of machine learning, they are taking an increasing part of MCU time becoming one of the main driving factors in the energy budget of the overall embedded system. We propose to integrate such algorithms into dedicated low-power circuits making the power consumption of the processing part negligible to the overall system. We provide the results of several implementations of a pre-trained physical activity classifier used in smartwatches and wristbands. The algorithm combines signal processing for feature extraction and machine learning in the form of decision trees for physical activity classification. We show how an in-silicon implementation decreases up to 0.1 µW the power consumption compared to 73 µW on a general-purpose ARM's Cortex-M0 MCU.

Atrial Fibrillation Detection on Low-Power Wearables using Knowledge Distillation.

The increasing complexity and memory requirements of neural networks have been slowing down the adoption of AI in low-power wearable devices, which impose important restrictions in computational power and memory footprint. These low-power systems are the key to obtain 24/7 monitoring systems necessary for the current personalized healthcare trend since they do not require constant charging. In this work, we apply Knowledge Distillation to our previously published convolutional-recurrent neural network for cardiac arrhythmia detection and classification. We show that the resulting network halves the memory footprint (138 K parameters) and the number of operations (1.84 MOp) compared to the baseline. By using Knowledge Distillation, this network also achieves significantly higher accuracy after quantization (increase in overall F1 score from 0.779 to 0.828) and is capable of running into a nRF52832 System-on-Chip from Nordic Semiconductors. This promising result lays the groundwork for deployment on resource-constrained embedded platforms such as micro-controllers of the ARM Cortex-M family, thus potentially enabling continuous detection of cardiac arrhythmias in low-power wearable devices.

Applying Lightweight Soft Error Mitigation Techniques to Embedded Mixed Precision Deep Neural Networks

Deep neural networks (DNNs) are being incorporated in resource-constrained IoT devices, which typically rely on reduced memory footprint and low-performance processors. While DNNs’ precision and performance can vary and are essential, it is also vital to deploy trained models that provide high reliability at low cost. To achieve an unyielding reliability and safety level, it is imperative to provide electronic computing systems with appropriate mechanisms to tackle soft errors. This paper, therefore, investigates the relationship between soft errors and model accuracy. In this regard, an extensive soft error assessment of the MobileNet model is conducted considering precision bitwidth variations (2, 4, and 8 bits) running on an Arm Cortex-M processor. In addition, this work promotes the use of a register allocation technique (RAT) that allocates the critical DNN function/layer to a pool of specific general-purpose processor registers. Results obtained from more than 4.5 million fault injections show that RAT gives the best relative performance, memory utilization, and soft error reliability trade-offs w.r.t. a more traditional replication-based approach. Results also show that the MobileNet soft error reliability varies depending on the precision bitwidth of its convolutional layers.

Supersingular Isogeny Key Encapsulation (SIKE) Round 2 on ARM Cortex-M4

We present the first practical software implementation of Supersingular Isogeny Key Encapsulation (SIKE) round 2, targeting NIST's 1, 2, 3, and 5 security levels on 32-bit ARM Cortex-M4 microcontrollers. The proposed library introduces a new speed record of all SIKE Round 2 protocols with reasonable memory consumption on the low-end target platform. We achieved this record by adopting several state-of-the-art engineering techniques as well as highly-optimized hand-crafted assembly implementation of finite field arithmetic. In particular, we carefully redesign the previous optimized implementations of finite field arithmetic on the 32-bit ARM Cortex-M4 platform and propose a set of novel techniques which are explicitly suitable for SIKE primes. The benchmark result on STM32F4 Discovery board equipped with 32-bit ARM Cortex-M4 microcontrollers shows that entire key encapsulation and decapsultation over SIKEp434 take about 184 million clock cycles (i.e., 1.09 seconds @168 MHz). In contrast to the previous optimized implementation of the isogeny-based key exchange on low-end 32-bit ARM Cortex-M4, our performance evaluation shows feasibility of using SIKE mechanism on the low-end platform. In comparison to the most of the post-quantum candidates, SIKE requires an excessive number of arithmetic operations, resulting in significantly slower timings. However, its small key size makes this scheme as a promising candidate on low-end microcontrollers in the quantum era by ensuring the lower energy consumption for key transmission than other schemes.