Arithmetic Unit Research Articles

Design of low power multi-ternary digit multiplier in CNTFET technology

This work introduces the method to implement energy efficient designs of arithmetic units such as a ternary full adder, ripple carry adder, single-trit multiplier and multi-trit multiplier using carbon nanotube field effect transistors (CNTFETs). A CNTFET unique feature of the threshold voltage variation by changing the CNT diameter, make it a suitable alternative for being employed in ternary logic designs. In designing the proposed circuits, decoder circuit functionality is realized by various threshold detector circuits tuned to a specific logical threshold voltage value. The multiplier circuit is designed by combing the capacitive logic and the minority function. In order to test the practicability of proposed circuits in cascaded circuits, multi-digit adder and multiplier circuits are constructed. The proposed multi-digit multiplier structure is based on classical Wallace multiplier and includes various optimized versions of adder and multiplier circuits. Extensive simulation has been done to examine the competency of proposed designs under different test conditions. The design of 3-trit multiplier formed by combing the proposed adder and multiplier circuits shows 16 times reduction in power consumption as well as energy consumption in comparison to previous multiplier design.

Implementation of Arithmetic unit for RNS using 2n-3 as Base

Residue Number System (RNS) is often used in Cryptographic applications. Choice of a unique base for RNS is an important factor in implementing RNS. Bit folding after multiplication is a commonly used method for implementing RNS. In this paper an architecture based on modulo 2 n -3 arithmetic is implemented. Each word of partial product is mapped once normal and then with one bit left shift with reference to the base number. The results are tabulated in terms of delay and area with Xilinx tool. Efficiency of implementation is compared with results available in literature.

Energy-Efficient Ternary Arithmetic Logic Unit Design in CNTFET Technology

This article presents the low-power ternary arithmetic logic unit (ALU) design in carbon nanotube field-effect transistor (CNFET) technology. CNFET unique characteristic of geometry-dependent threshold voltage is employed in the multi-valued logic design. The ternary logic benefit of reduced circuit overhead is exploited by embedding multiple modules within a block. The existence of symmetric literals among various single shift and dual shift operators in addition and subtraction operations results in the optimized realization of adder/subtractor modules. The proposed design is based on the notion of multiplexing either arithmetic, logical or miscellaneous operations, depending upon the status of input selection trits. The results obtained by the synopsis HSPICE simulator with the Stanford 32 nm CNFET technology illustrate that the proposed processing modules outperform their counterparts in terms of power consumption, energy consumption and device count. The proposed methodology leads to saving in power consumption and energy consumption (PDP) of 62% and 58%, respectively, on the benchmark circuit of the ALU [full adder/subtractor (FAS)]. Furthermore, for the 2-trit multiplier design, the enhanced performance at the architecture and circuit level is achieved through the optimized designs of various adder and multiplier circuits.

Low Power Full Adder Design Using PTM Transistor Model

Abstract At present the processing power of the digital electronic chip is enormous and that has been possible because of the continuous improvement of the design methodology and fabrication technology. So, the data processing capability of the chip is increased significantly. Data processing in the electronic chip means the arithmetic operation on that data. For that reason, ALU is present in any processor. Full adder is one of the critical components of arithmetic unit. Improvement of the full adder is necessary for improving the computational performance of a chip. In order to design an efficient full adder, designer should choose an appropriate logic style. In this research, two new model of full-adder circuits are designed and analyzed using Pass Transistor logic in order to reduce power consumption and increase operational speed. The first proposed adder consists of 8 transistors and the second one consists of 10 transistors. LTSPICE is employed for simulating the proposed circuits using16nm low power high-k strained silicon transistor model. The overall performance of the proposed adder circuits and comparative results demonstrate the superiority of the proposed model.

Multilayer Structure of a New Portable, Low-Cost and Reversible Arithmetic and Logic Unit using High-Speed and Low-Power “QCA” Technology with Good-Scalability.

All nano-technologies including “QCA” (Quantum-dot Cellular Automata) is widely used in today’s world to reduce the power dissipation, area and delay. “QCA” is a magnify technology with huge advantages such as: high-speed, high-density, faster-switching and higher clock-frequency which is rapidly used for Integrated-Circuit (“IC”) design. Quantum-dot Cellular Automata is an useful and appropriate alternative of the “CMOS-technology” because of its various advantages such as: it’s high-frequency, less power leakage and less required area. An “ALU” (arithmetic and logic unit) is applying for all types of arithmetic-logical performances and it widely used in digital circuits for all types of arithmetic and logical operations. The reversible-Logic an authentic solution in low-power and low-cost technology. This paper presents a latest 3-D or multilayer structure of ALU using reversible-computing and also non-reversible logic which gives a comparative outcome with low supply-power and delay. The complexity of the formation and the engrossed size of this model is low. ‘AND-Gate’, ‘OR-Gate’ ,‘XOR-Gate’ and the reversible ‘TSG-Gate’ and also the non-reversible model of “Full-Adder” are used to design the suggested model of this paper through the “QCA Designer” software (for simulation).This design reduce the size of the model up to 0.11 μm2 with three layers which is also compared to the formation in the “Xilinx” software.

The Mixed Logic Style based Low Power and High Speed One-bit Binary adder for SOI designs AT 32NM Technology

Binary adders are the fundamental building blocks to construct Data Processing arithmetic units. A novel one-bit full adder is presented in this paper which is designed by Mixed logic design style. In addition to small size transistors and reduced transistor activity compared to conventional CMOS (Complementary Metal Oxide Semiconductor) gates, it provides the priority between the High logic and Low logic for the computation of the output. Various logic topologies are used to design the one-bit full adder like High-Skew(Hi-Skew), Low-Skew(Li-Skew), TGL (Transmission Gate Logic) and DVL (Dual Voltage Logic). This new approach gives the better operating speed, low power consumption compared to conventional logic design by reducing the transistors activity and by improving the driving capability. This Mixed logic style provides 83.53% average power consumption and Propagation Delay of 14.02% at 0.8v. The H-SPICE simulation tool is used for construction and evaluation of the Full adder logic at different voltages. The 32nm model file is used for MOS transistors.

A 13.34μW Event-Driven Patient-Specific ANN Cardiac Arrhythmia Classifier for Wearable ECG Sensors.

Artificial neural network (ANN) and its variants are favored algorithm in designing cardiac arrhythmia classifier (CAC) for its high accuracy. However, the implementation of ultralow power ANN-CAC is challenging due to the intensive computations. Moreover, the imbalanced MIT-BIH database limits the ANN-CAC performance. Several novel techniques are proposed to address the challenges in the low power implementation. Firstly, continuous-in-time discrete-in-amplitude (CTDA) signal flow is adopted to reduce the multiplication operations. Secondly, conditional grouping scheme (CGS) in combination with biased training (BT) is proposed to handle the imbalanced training samples for better training convergency and evaluation accuracy. Thirdly, arithmetic unit sharing with customized high-performance multiplier improves the power efficiency. Verified in FPGA and synthesized in 0.18μm CMOS process, the proposed CTDA ANN-CAC can classify an arrhythmia within 252μs at 25MHz clock frequency with average power of 13.34μW for 75bpm heart rate. Evaluated on MIT-BIH database, it shows over 98% classification accuracy, 97% sensitivity, and 94% positive predictivity.

High-efficiency and integrable DNA arithmetic and logic system based on strand displacement synthesis

Powerful information processing and ubiquitous computing are crucial for all machines and living organisms. The Watson-Crick base-pairing principle endows DNA with excellent recognition and assembly abilities, which facilitates the design of DNA computers for achieving intelligent systems. However, current DNA computational systems are always constrained by poor integration efficiency, complicated device structures or limited computational functions. Here, we show a DNA arithmetic logic unit (ALU) consisting of elemental DNA logic gates using polymerase-mediated strand displacement. The use of an enzyme resulted in highly efficient logic gates suitable for multiple and cascaded computation. Based on our basic single-rail DNA configuration, additional combined logic gates (e.g., a full adder and a 4:1 multiplexer) have been constructed. Finally, we integrate the gates and assemble the crucial ALU. Our strategy provides a facile strategy for assembling a large-scale complex DNA computer system, highlighting the great potential for programming the molecular behaviors of complicated biosystems.

Design Of Area Efficent 32 Bit Arithmetic And Logic Unit (Alu) For Dsp Processors

Almost every electronic gadget contains the Digital signal processor (DSP) unit for the purpose of computations, whose role couldn’t be specified with smaller words. Gadget’s performance, efficiency and the importance could be measured with how best the specifications of the processors are. Arithmetic and Logical Unit (ALU) is the key circuit for any DSP processors, where large data computations can be performed. Hence, the ALUs design should be include high performance and large data handling capacity. An ALU is a digital electronic circuit that performs arithmetic and bitwise operations on integer binary numbers. The conventional ALU designs, design complexity rate proportionally increases with the performance demand. In this paper, an attempt has been given to design a low complex ALU with improved performance. Sub circuits designs comprise with new approaches to make the simple designs for higher performance of ALU. A 32 bit ALU design procedure has been demonstrated in this paper. For design, 90 nm CMOS technology and CADENCE virtuoso tools used.

Reducing Regression Time in Neural Network us-ing Nth Absolute Root Mean Error

Neural networks require a large dataset to learn features, and this takes high computational power, even using high end Graphical Processing Units (GPUs) some use cases might require days of continuous training. This can be solved either by making hardware specific changes to code or by replacing the algorithm used. In this paper we propose a novel loss function called Nth Absolute Root Mean Error (NARME) which speeds up the training process for a set of supervised learning problems, specifically regression (which is a problem in which we predict value of a continuous variable). In this function, we take nth root of the absolute difference between the predicted and the actual output, then calculate the mean over the entire set of data points available in the dataset, thus in a way starting at a much lower point in the gradient descent curve than other commonly used regression losses. The loss function (NARME) places the value of loss after the first iteration to a point that is closer to the minima (which is the goal of the training process), and then takes small number of descent steps in the n-dimensional space to reach the global minima. NARME has been found to work with commonly used neural network architectures and is shown to work exceptionally well with Neural Arithmetic and Logic Unit cell type networks. The usage of this type loss function in regression problems helps speed the training process by a factor of ten in most of the cases, due to the small number of steps it requires to reach the minima.

R-Accelerator: An RRAM-Based CGRA Accelerator With Logic Contraction

In this paper, a novel RRAM-based reconfigurable accelerator (R-accelerator) design is proposed, which makes special use of existing RRAM device for high-efficient reconfigurable application-specific computing. The proposed R-accelerator design consists of RRAM-based arithmetic unit (AU) array, fully integrated into commercial EDA design tools. A significant area saving is achieved compared with conventional digital counterpart due to the proposed logic contraction technique, as well as saving of storage space and routing congestions. For enabling the optimization of the AU array, this paper also proposes a systematical method on the synthesis of the AU array under routing channel constraint for application-specific designs. Two automatic mapping algorithms, including simultaneous mapping and incremental mapping algorithms, are proposed and compared. The experiments using 45-nm CMOS technology on a case study of dynamic time warping example and general benchmark programs show up to 49% area reduction and 28% performance enhancement using the proposed R-accelerator technique compared with conventional application-specified integrated circuit (ASIC) design.

New Optimized Reconfigurable ALU Design Based on DG-CNTFET Nanotechnology

<p>The heart of the microprocessor and responsible for the execution of logical and arithmetic operations, the arithmetic and logical unit is constantly optimized. The performance is improved to allow the development of more powerful and smaller circuits. This paper describes simple ALU but contains the essentials functions. It is a reconfigurable ALU based on double-gate carbon nanotube field effect transistor (DG-CNTFETs). This transistor has an interesting property, it can switch from p- to n- type behavior and vice-versa dynamically. This opens the opportunity for building novel and complex functions in fine-grain reconfigurable logic inaccessible to MOSFETs and reaching a good performance levels. In literature there are several problems related to signal quality. In this paper, we will propose a new solution that allows us to improve the quality of the output signal without affecting the number of transistors used. This improves the overall performance of ALU. We will show the improvement in signal level and quality. First, an overview of carbon nanotube field-effect transistor (CNTFET) and state of the art Reconfigurable ALU based on DG-CNTFET is given. Then an explication of signal integrity issues of the actual Reconfigurable DG-CNTFET cell is done. After we will present and explain the proposed solution. The solution is first applied on the cnt_9T circuit then will show its effect on the ALU. Finally, a performance comparison is made.</p>

32-Bit One Instruction Core: A Low-Cost, Reliable, and Fault-Tolerant Core for Multicore Systems

Abstract Occurrences of both transient and permanent errors pose a major challenge in the wake of burgeoning growth in transistor density. Manufacturing defects and process variants lead to permanent faults, thereby lowering processor yields. In the arithmetic logic unit, single permanent faults result in the absolute failure of processors. Both low-energy neutrons and alpha particles from the cosmos induce transient errors by altering the state of the transistor. In wake of the implications, we postulate a new, reliable, fault-tolerant, low-cost 32-bit one instruction core (OIC) for a multicore system. “Low cost” here means low power and lower area. Notably, 32-bit OIC provides fault-free execution with triple redundant subtractors with one additional subtractor. It only executes one instruction called subleq repetitively in order to emulate the faulty instructions migrated into it by other cores. Hardware synthesis is undertaken to estimate leakage power, dynamic power, critical path delay, and area. The low-power 32-bit OIC consumes 1.3 mW, with a die area of 8,122 μm2. Apart from also adding performance overhead, 32-bit OIC outperforms its competitors with regard to reliability, area, power, and critical path delay. Additionally, the probabilistic estimate with link vulnerability factor—as a new parameter—is introduced to assess the effect of soft errors or transient faults on interconnect wires, which are then quantitatively analyzed to illuminate the resilience of 32-bit OIC hardware structure. Additionally, we propose new design alternatives (including existing ones) for heterogeneous multicore systems in order to develop low-cost solutions with a primary focus on reliability.

New Optimized Reconfigurable ALU Design Based on DG-CNTFET Nanotechnology

<p>The heart of the microprocessor and responsible for the execution of logical and arithmetic operations, the arithmetic and logical unit is constantly optimized. The performance is improved to allow the development of more powerful and smaller circuits. This paper describes simple ALU but contains the essentials functions. It is a reconfigurable ALU based on double-gate carbon nanotube field effect transistor (DG-CNTFETs). This transistor has an interesting property, it can switch from p- to n- type behavior and vice-versa dynamically. This opens the opportunity for building novel and complex functions in fine-grain reconfigurable logic inaccessible to MOSFETs and reaching a good performance levels. In literature there are several problems related to signal quality. In this paper, we will propose a new solution that allows us to improve the quality of the output signal without affecting the number of transistors used. This improves the overall performance of ALU. We will show the improvement in signal level and quality. First, an overview of carbon nanotube field-effect transistor (CNTFET) and state of the art Reconfigurable ALU based on DG-CNTFET is given. Then an explication of signal integrity issues of the actual Reconfigurable DG-CNTFET cell is done. After we will present and explain the proposed solution. The solution is first applied on the cnt_9T circuit then will show its effect on the ALU. Finally, a performance comparison is made.</p>

Trinary magnitude comparator using SLM based Savart plate

The demand of present technology inviting the popularity of multivalued optical computation system to coup up with the latest scenario of ultrahigh processing speed and handling large amount of data The magnitude comparator is the heart of the arithmetic and logic unit (ALU) in any logical processing and computing system. In this paper, a trinary magnitude comparator circuit has been proposed and implemented with modified trinary number (MTN) system. Optical tree architecture (OTA) of the proposed circuit has been realized reasonably using Savart plate and spatial light modulators (SLM). A simulation algorithm has also been developed and implemented to prove the authenticity of the proposed circuit through the simulation.

The Mixed Logic Style based Low Power and High Speed 3-2 Compressor for ASIC designs at 32nm Technology

Compressors are the fundamental building blocks to construct Data Processing arithmetic units. A novel 3-2 Compressor is presented in this paper which is designed by Mixed logic design style. In addition to small size transistors and reduced transistor activity compared to conventional CMOS (Complementary Metal Oxide Semiconductor) gates, it provides the priority between the High logic and Low logic for the computation of the output. Various logic topologies are used to design the 3-2 compressor like High-Skew(Hi-Skew), Low-Skew(Li-Skew), TGL (Transmission Gate Logic) and DVL (Dual value Logic). This new approach gives the better operating speed, low power consumption compared to conventional logic design by reducing the transistors activity, improving the driving capability and reduced input capacitance with skew gates. Especially the Mixed logic style-3 provides 92.39% average power consumption and Propagation Delay of 99.59% at 0.8v. The H-SPICE simulation tool is used for construction and evaluation of compressor logic at different voltages. 32nm model file is used for MOS transistors

Energy-efficient Design of MTJ-based Neural Networks with Stochastic Computing

Hardware implementations of Artificial Neural Networks (ANNs) using conventional binary arithmetic units are computationally expensive, energy-intensive, and have large area overheads. Stochastic Computing (SC) is an emerging paradigm that replaces these conventional units with simple logic circuits and is particularly suitable for fault-tolerant applications. We propose an energy-efficient use of Magnetic Tunnel Junctions (MTJs), a spintronic device that exhibits probabilistic switching behavior, as Stochastic Number Generators (SNGs), which forms the basis of our NN implementation in the SC domain. Further, the error resilience of target applications of NNs allows approximating the synaptic weights in our MTJ-based NN implementation, in ways brought about by properties of the MTJ-SNG, to achieve energy-efficiency. An algorithm is designed that, given an error tolerance, can perform such approximations in a single-layer NN in an optimal way owing to the convexity of the problem formulation. We then use this algorithm and develop a heuristic approach for approximating multi-layer NNs. Classification problems were evaluated on the optimized NNs and results showed substantial savings in energy for little loss in accuracy.

Design of Reversible Arithmetic Logic Unit with Built-In Testability

Editor’s note: This article presents an advanced reversible arithmetic logic unit with built-in testability for single bit-flip errors. —Shreyas Sen, Purdue University

Performance Evaluation of New Adder Designed for Electronic Circuits

Arithmetic and Logic Unit (ALU) is the important module in any digital system utilized in the current world applications. Adder plays major role in the construction of any ALU. Multipliers can also be designed with the help of continuous addition. The efficient design of adders is very much needed for the efficient ALU design. Parallel prefix adder has been chosen in this research because of its fastest computation and efficiency. Kogge Stone, Sklansky, Ladner Fischer, Brunt Kung, Han-Carlson and Knowles are the adders discussed in this research. Further, the combinations of any two adders have also been tested for the best efficiency in terms of power consumption and delay utilisation. From the many combinations, it is found that the proposed combination of Bruntkung and SKlansky (BSK) adder performs excellent with the power consumption of 25011.22 nW and delay of 1243 pS.

Radix-10 Fixed Point Division Hardware

Standardization of decimal floating-point formats by IEEE in IEEE 754-2008 Standards fuelled the interest on decimal floating-point architectures among the global research community. Although decimal arithmetic architecture research attracted computer scientists for the last two decades, the major thrust was observed past the year 2008. Multiple proposals have been witnessed for decimal arithmetic units, mostly adders/subtractors, and multipliers. Very few designs have been proposed in the division domain. This article proposes decimal division hardware based on sutras from Vedic Mathematics, the ancient mathematics system. We present a Reduced Magnitude Divisor Generator which converts each digit of the actual divisor into a reduced digit set [-5, 5] using a unique combination/modification of the Vedic Sutras. The divisor digit magnitude reduction also minimizes the product set of multiplication as the single-digit multiplier belongs to the reduced digit set [0, 5] barring the sign. The sign of the dividend or the divisor is not attended during division as a simple XOR operation on the two signs provides the sign of the quotient. Peer comparison has exhibited better results for our design in terms of space and time.